| FIGURE 1 |
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| The delayed clock signal makes the flip-flop sample the clock on the next cycle to ensure that the clock exists. If the clock fails, the circuit sets the CLOCK FAIL OUT flag. |
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| FIGURE 1 |
|
| The delayed clock signal makes the flip-flop sample the clock on the next cycle to ensure that the clock exists. If the clock fails, the circuit sets the CLOCK FAIL OUT flag. |
back |