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Design IdeasDecember 19, 1996 |
Many of today's digital systems
require multiple clock domains as well as the ability to switch between them on
the fly without producing glitches. 
Listing
1 consists of synthesizable VHDL code for such a circuit. In the circuit,
two lines choose from among four input clocks to produce an output clock. The
internal logic consists of a 2-to-4 line decoder, four identical clock-enabler
logic blocks, and a 4-to-1 line multiplexer. You can easily customize the
circuit for your application once you understand the basic concept.
The decoder decodes the two select signals that select one of the four clocks. The clock-enabler logic synchronizes a decoder output of the decoder to its corresponding clock and generates a clock enable signal. This enable signal, which occurs on the rising edge of its respective clock, goes active only after you remove the clock enable signals from the other clock-enabler logic blocks. Now, simply OR-ing this signal with the corresponding clock creates a glitch-free clock. This enable signal also controls the multiplexer that drives out the selected clock.
Simulation results show that the circuit does not generate glitches when switching from one clock domain to another. Instead, the circuit incurs a dead period, which corresponds to the time it takes to turn off the old clock and turn on the new one. You can download the VHDL code and the postscript files of simulation waveforms from EDN's Web site: /. At the registered-user area, go into the "Software Center" to download the file from DI-SIG, #1965. (DI #1965)
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