March 13, 1998

Inexpensive relays form digital potentiometer

Robert Perrin, Z-World, Davis, CA

A project posed the challenge of replacing existing analog potentiometers (used to set brightness and contrast levels) in video monitors with digitally controlled potentiometers. The different brands and models of monitors presented widely varying voltages across the potentiometers. The design had to

• accept digital controls,
• be purely resistive,
• tolerate 60V dc or ac between any two points,
• be able to dissipate 1W,
• be scalable for future systems, and
• have high isolation between the digital controller and the simulated potentiometer.

Also, during switching, the wiper could not become open-circuited, and it had to be able to travel end-to-end.

Existing digitally controlled potentiometers were not up to the task. FET switches faced special challenges with the ac-voltage isolation criterion. The design in Figure 1 uses inexpensive relays to build a digitally controlled potentiometer. The relays switch their respective resistors above or below the tap. With all the relays de-energized, the potentiometer has the configuration shown in Figure 2a. With all the relays energized, the relay takes the form shown in Figure 2b. The resistors are weighted in a R_TOTAL/2ⁿ relationship. This weighting gives a good approximation of a linear taper with 32 (2⁵) positions. Table 1 shows the selection of resistor values.

The circuit uses a 74HC374 latch and MPS2222A npn transistors to interface the relays to the system CPU (Figure 3). The primary disadvantages of the method are board space and cost. However, for the monitor application, the circuit proved flexible and reliable. Applications that require replacing existing potentiometers or rheostats are potential candidates for this circuit. For example, you could replace a high-power rheostat with the circuit if you select relays and resistors with suitable current ratings.

Switched-capacitor regulator provides gain

Jeff Witt, Linear Technology Corp, Milpitas, CA

Linear voltage regulators become inefficient when the input voltage is much higher than the regulated output. The circuit in Figure 1 dramatically increases efficiency when the input voltage is more than twice the desired output; for example, using 12V to obtain a regulated 3.3 or 5V. You usually use a switched-capacitor voltage inverter to generate a negative supply voltage from a positive input voltage. The negative-supply current is equal to the current drawn from the input. By swapping the roles of the ground and output pins, the inverter in Figure 1 divides the input voltage by two. It also doubles the current from the input to the output, thereby providing much better efficiency than does a linear regulator.

Figure 2 illustrates the circuit's operation. An internal oscillator alternately closes and opens four switches. In the first half-cycle, switches 1 and 2 close, and current flows from the input to the output, charging C₁. In the second half- cycle, switches 3 and 4 close, discharging C₁ into the output. The current delivered to the output is continuous and equal to twice the average input current. Because the current is continuous, the output-voltage  ripple is low. Note that you do not need to match C₁ and C_OUT, because their voltages equalize on each cycle.

Figure 3 shows the actual circuit. IC₁, an LT1054 switched-capacitor voltage converter and regulator, modulates the current (through switch 1 of Figure 2) to regulate the output. A servo loop keeps the potential  at the FB pin equal to the potential at the GND pin. The circuit can deliver 200 mA at 5V from an input of 11.2 to 13V. Typical efficiency is 74%, compared with 42% for a linear regulator. More important, dissipation decreases from 1.4W for a linear regulator to 0.35W, a figure that IC₁'s eight-pin, surface-mount package can easily handle. For a 200-mA, 3.3V output, the circuit is 49% efficient, compared with a linear regulator's 27%, with power dissipation reduced from 1.8 to 0.7W. A 6.2 ohm resistor in series with C₁ shares the dissipated power with the LT1054; the circuit needs no heat sink.

Precision current sink costs less than $20

Carlos Barberis, Bartek Technologies, Haverhill, MA

If you often need a simple active load (constant-current sink), you can benefit from the simple circuit in Figure 1. The need often arises to measure the life of a battery or other power device under constant-load conditions. The easy-to-build and inexpensive circuit in Figure 1 is a handy addition to your arsenal of test fixtures. You can build the circuit for less than $20. The most expensive parts are the vernier knob and the multiturn potentiometer. You can build the active load into a miniature enclosure with banana-jack connectors. The vernier control allows you to directly set current from 1 mA to 1A by simply dialing the desired set current. Without the vernier and multiturn potentiometer, you could build the circuit for less than $10, but you then lose the advantage of a calibrated, stand-alone test box.

The circuit is a precision current sink with typical current regulation of better than 0.5% for a 3 to 40V compliance voltage. R₄ is a sensing resistor; its voltage drop servos the input voltage to IC_1A. The wiper of the vernier potentiometer sets the input voltage, discounting any amplifier offset errors. The offset could be as high as 2 mV in a run-of-the-mill LM10, translating to a 2-mA error between the set current and the current flowing in R₄. The reference amplifier, IC_1B, is a gain-of-5 stage that provides a 1.00V reference on the high side of the current-setting potentiometer. The voltage-to-current transfer function is thus 1A/1V. You can change the transfer function to fit your needs.

Although the current-control mechanism allows the output of the current source to approach zero, the additional currents consumed by the circuit (approximately 400 µA) establish the baseline current. Therefore, you set the bottom of the potentiometer via R₃ to start at approximately 1 mA. Under normal operation, a current setting of 1 to 300 mA maintains the setpoint within 0.5% with 3 to 40V compliance. Currents above 300 mA require 3 to 5V for compliance. The circuit maintains a 1A current within 300 µA from 4.9 to 40V or within 0.001% tolerance (Figure 2). You could lower the initial regulation point by one diode junction by removing D₁, whose sole purpose is to prevent destruction of the active circuitry when you connect the power supply backward.

The principal sources of error in the circuit are the amplifier offset, the tolerance of the reference voltage, the tolerance of R₄, and the fact that the current includes various branch currents other than the controlled current in the sensing resistor. These branch currents add up to approximately 400 µA, or roughly five times lower than the offset-voltage error. You can consider the error negligible for settings of 10 mA and above. The most important issue for long-term stability is efficient heat removal from the current-regulating transistor, Q₁. The transistor needs an appropriate heat sink; the choice of heat sink depends on the current ranges you need.

The element that encounters the largest voltage drop at a given current is the hottest. Q₁ dissipates V_IN­1W for any given input voltage when operating at 1A. If you plan to use the load on a continuous basis, for example at 1A, with a 30V input, Q₁ dissipates 29W; R₄ consumes 1W. Q₁ would thus need a hefty extruded heat sink.

Simple logic probe uses bicolor LED

Mark Shill, Burr-Brown Corp, Tucson, AZ

When probing digital logic levels on a circuit board, locating the indicator of the logic level near the probe tip is convenient, so that you can keep both the indicator and probe tip constantly in sight. When using a handheld DVM or oscilloscope probe, you must momentarily look away to read the logic level. In that instant, the   probe can slip and cause a short circuit. The circuit in Figure 1a implements a simple handheld logic probe using just a few components. This probe can measure high, low, and high-impedance logic states, in addition to indicating switching logic states. This probe is useful for quick measurements of dc logic levels. You can use a similar probe circuit (Figure 1b) for 3V CMOS logic.

The circuit centers around the OPA2340 dual rail-to-rail op amp and a Radio Shack 276-012 bicolor LED. The forward voltage for the red and green LEDs are 2 and 2.1V, respectively. Op amp IC_1A derives a buffered 2.5V reference output from the 5V supply, and R₃ limits the current to the LED when it is on. IC_1B buffers and amplifies the probed logic signal to a 0 to 5V output level. R₄ and R₅ set a reference level for the positive input of IC_1B for the case of a high-impedance level. When a  logic high is present, the green LED lights; a logic low lights the red LED. When a high-impedance state is present, the LED is off.

The output voltage transfer function of IC_1B is

which makes V_LED=V_B­2.5V. The values of R₆, R₇, and R₈ are such that V_B limits at the positive or negative power-supply rail when V_PROBE is at the logic family's minimum low or high level, respectively. Figure 2 shows the volt- age-transfer function for V_B. When V_B limits at the rail voltage, the LED lights red or green, depending on the probed logic level. When V_B is within 0.5V of the negative rail, the red LED turns on; when V₂ is within 0.4V of the positive rail, the green LED turns on. If the probe measures a high-impedance state, voltage-divider resistors R₄ and R₅ set the positive input of IC_1B, and the voltage across the LED is approximately 0V.

In Figure 1b, the output of IC_1B feeds into IC_1A's inverting input. For the resistor values in Figure 1b, the transfer function for IC_1A is V_A=­V_B+3V, thus making V_LED=2V_B­3V.

DC power wire also carries clock or data

Mike Hardwick, Decade Engineering, Turner, OR

A high-side current-sense amplifier, IC₁, offers a simple method of combining low-speed clocks or other signals with dc power in cables between subsystems (Figure 1). Designed for monitoring charge and discharge current in secondary batteries, IC₁ outputs a current of 0.5 mA per amp of load current flowing through its internal sense resistor while rejecting common-mode supply-voltage noise. The on-chip sense resistor handles as much as 3A of continuous current. The IC accommodates power-supply voltages from 3 to 36V.

Figure 1 depicts a subsystem that receives power from its host system and simultaneously transmits a clock signal back on the same wire. The circuit uses the clock in the remote system to modulate power-supply current via an open-collector driver or discrete transistor and R_MOD, a switched load resistance. In the host system, IC₁ develops a voltage across R_IV, which represents the instantaneous sum of supply current and modulation current. R_INTEG and C_INTEG filter this voltage, biasing the comparator's reference pin to a level that tracks average power-supply current. As the signal swings above and below this reference level, the comparator outputs the recovered clock. R_HYST adds a small amount of hysteresis to ensure clean clock recovery.

IC₂, which comes in an SOT23-5 package, is a CMOS comparator with a rail-to-rail input range. This range allows you to choose R_IV with relative freedom--expect about 1V/A of load current for each 2 kiloohms of resistance. The input offset of low-grade versions of IC₂, an LMC7211, can be as much as ±18 mV. Thus, select R_MOD and R_IV to produce 50 mV or more of modulation on R_IV, and then choose R_HYST to obtain a few additional millivolts of shift at this node when the comparator changes state. None of these values is critical.

For this scheme to work as expected, the power-supply current to the remote system must be relatively constant, except for the intentional modulation. Slow power-supply current variations do not cause problems, as long as you choose the integrator components with care. The integrator RC product should be about 10 times the clock period. It's convenient to choose R_INTEG of approximately 1 Megaohm when using CMOS comparators, such as IC₂. You can then use ceramic or plastic-film capacitors for C_INTEG, thus minimizing the risk of failure due to capacitor leakage.

The circuit can also transmit data if the data contains little dc bias variation or if you replace the integrator components with a fixed bias source. This change means, of course, that no significant power-supply current change is allowable after calibration.

IC₁'s output rise and fall times measure approximately 4 µsec, a figure similar to IC₂'s response-time specification. The remote system's power-supply bypass capacitance may impose an upper bound on the clock rate because this capacitance limits the modulation rate of the supply current. This time constant is C_LOAD×(R_SENSE+R_CABLE). R_SENSE is less than 0.07 ohms*.qrk

in IC₁, and the cable's series resistance depends on the application. You must add the equivalent series resistance of the power source, connectors, and any other associated resistive elements to R_SENSE in this calculation if you're pushing the envelope of the circuit's performance. 

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