UBM Tech
UBM Tech

Testing safety-critical automotive parts

-June 18, 2013

Using this hybrid approach also gives you several ways to improve test efficiency during manufacturing test. Pseudo-random patterns can be used first to cover the faults that are easier to detect. Because stored patterns are no longer needed for these faults, additional tester pattern storage becomes available for targeting faults that are more difficult to detect. The hybrid solution can also reduce the total test time for a complex hierarchical design. Each core is equipped with its own hybrid test infrastructure, which allows it to be tested independently of other cores.  When they can be tested independently, they can be tested in parallel, thus reducing overall test time.

Consider, for example, an automotive IC design with four cores. If only ATPG compression were available, then the four cores would have to share the available tester pattern application bandwidth. Each core could either be tested sequentially using all available tester channels or all cores could be tested in parallel with each core using a subset of the channels. However, if each core has both ATPG compression and logic BIST available, then the test for each core can be divided into two phases—ATPG compression used in one phase and logic BIST in the other. With this separation, the entire chip can be tested in two phases.  In the first phase, two cores use ATPG compression, and the other two use logic BIST. In the second phase, the situation is reversed. The advantage now is that in each phase, only two cores are sharing all available tester channels, as logic BIST does not require patterns from the tester. This means the bandwidth to each core is doubled, and, hence the test time is reduced by half.

The hybrid compression/LBIST solution plays another critical role related to the ISO 26262 standard. The LBIST capability provides support for in-system test of the device logic. This represents a key capability necessary for addressing the reliability requirements defined by the standard. The LBIST capability can be combined with existing memory BIST capabilities to provide in-system test coverage for most, if not all, of the design. All of the BIST capabilities can generally be accessed through the standard IEEE 1149.1 TAP controller interface. This dedicated interface is sometimes not accessible in-system. To accommodate in-system access, the TAP controller can be enhanced to also support a generic CPU interface that translates between parallel read/write CPU operations and the serial bit sequences required by the TAP protocol (see Figure 2).

Figure 2: A CPU-based BIST access illustration.

Meeting the quality and reliability requirements of the ISO 26262 and other automotive electronics standards will only become more difficult as device sizes and complexities continue to grow. New advanced test technologies such as cell-aware ATPG and hybrid compression/LBIST provide some key building blocks towards ensuring compliance to the new standards.

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Author Profile: Stephen Pateras

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