Design Con 2015

Simple SPICE phase locked loop (PLL)

-November 06, 2007

IC designer Don Sauer saw my blog about the difficulties of simulating PLLs and sent me a SPICE file (zip) of a basic PLL that you can play with. Don writes:

I have a simple spice netlist for a PLL where it possible to watching lock in on the time domain without too much trouble. This is not a optimize PLL. But it could be a good starting point for the development of one. See my various source files in the enclosed directory labeled "PLL_Spice". The pdf file shows the transient waveforms..

The pdf also has some of Don’s ASCII schematics, which he used to include in emails when we both worked at National Semiconductor. They take a little getting used to but being able to send schematics in plain text is a real benefit since the Spam filters seem to delete every file with an attachment. Plain text emails with no links almost always go through. I assume Don picked up the ASCII schematic bug back in the old newsgroup and bulletin board days, when you had to use ASCII.

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