SiSoft publishes a resource guide for IBIS-AMI model development.
The vivacious Ronda Katz over at SiSoft, the people who invented the IBIS-AMI (input/output buffer information specification - algorithmic modeling interface) has sent a press release about Opal, their resource guide for developing IBIS-AMI simulation models of serdes PHYs (serializer/de-serializer physical-layer devices). IBIS is a time-domain look-up table that represents the outputs of fast digital pins. You use it as a stimulus for the pins in simulations, so you can characterize how they will act. Think of IBIS as a SPICE model without the model, it is just the drive levels of a pin. Things like rise and fall time, ringing, and overshoot/undershoot. With FPGAs having hundreds of outputs, software programs could not do transistor-level simulations of all those pins fast enough, so you use these simpler IBIS models. That helps you figure out how much of a one or a zero you get after the signal goes over a PCB trace and maybe a backplane connector. That is represented in the eye-diagram that the simulator makes, or you can measure with a scope. From the eye diagram you can use MatLab or these SiSoft type of tools to infer bit-error-rate (BER), which is really what your spec is.
The problem is that serializers now have preemphasis circuits, like a tone control or RIAA curve that emphasizes the high-frequency components of the signal that you know will get attenuated as the signal travels over the circuit board. The de-serializers have equalizers, which also put a complex digital filter on the received signals, in order to improve the eye diagram and the resulting BER. Some of these equalizers are adaptive, changing their parameters over time. Putting a scope probe on the traces, even if you had some magic probe that wouldn’t affect the signals with capacitive loading and stub problems, will not tell you the real performance of the channel, since the scope normally couldn’t perform the algorithms on the waveform that receiver (de-serializer) chip does. That is the cool thing about the AMI. It allows a chip company to provide us with some code that describes how these preemphasis circuits and equalizers work. That code doesn’t give away the algorithm. Now renegade Chinese Gypsy pirates can’t steal the intellectual property and sell an equivalent chip for 3 cents, since they didn’t need to pay a staff of engineers like us to develop the algorithm. I describe the AMI and the whole high-speed serial link design challenge in my recent article on signal integrity. With AMI, both your scope and your software simulation can account for the algorithms inside the chips, and tell you the true robustness and BER of your high-speed serial link. Mentor Graphics, Cadence, Zuken, Ansoft, and Sigrity, among many others, can use these AMI models in their software simulators. Kudos to SiSoft for releasing this specification for everyone to use.