# Feedback and Impedances

Negative feedback has a profound impact on the input and output impedances of a circuit. For an intuitive feel, consider the popular op amp circuit of Figure 1, which we assume to be a well-designed circuit with *r _{i}* >>

*R*

_{1}//

*R*

_{2}and

*r*<<

_{o}*R*

_{1}+

*R*

_{2}. To find the closed-loop input resistance

*R*, apply a test voltage

_{i}*v*, find the ensuing current

_{I}*i*, and then let

_{I}*R*=

_{i}*v*/

_{I}*i*. So long as the gain

_{I}*a*is suitably high,

_{v}*v*will be very small, in turn making

_{D}*i*quite small and therefore

_{I}*R*quite large. Indeed,

_{i}

where *A* = *a _{v}*/(1 +

*T*) is the closed-loop gain, and

*T*≈

*a*/(1 +

_{v}*R*

_{2}/

*R*

_{1}) is the loop gain [1]. Consequently,

To find the closed-loop output resistance *R _{o}*, subject the output port to a test current

*i*, find the ensuing voltage

_{O}*v*, and then let

_{O}*R*=

_{o}*v*/

_{O}*i*. Again,

_{O}*v*is bound to be very small, implying a very small current through

_{D}*R*

_{1}and, hence, through

*R*

_{2}. So, virtually all of

*i*will flow right into

_{O}*r*, giving

_{o}

so

**Figure 1.** **Circuits to find the closed-loop resistances R_{i} and R_{o} of the series-shunt configuration.**

The above transformations reveal typical negative-feedback features, namely, the tendency to *raise *the impedance of a *series*-type port and to *lower* the impedance of a *shunt*-type port. In fact, two-port analysis (TPA) predicts the impedance transformations

where *z _{pa}* is the open-loop impedance presented by the port under scrutiny,

*T*is the loop gain,

_{TP}*Z*is the closed-loop impedance, and we use the exponent +1 in the

*series*case, and –1 in the

*shunt*case. As discussed previously [2], TPA requires that we identify which of the four feedback topologies is in use so we can suitably manipulate the basic amplifier to find

*T*as well as its open-loop impedances

_{TP}*z*and

_{ia}*z*.

_{oa}Return-ratio analysis (RRA) expedites the process by expressing the impedance *Z* between *any two nodes* (not just the nodes of the input port or the output port) via *Blackman’s Impedance Formula*

where *z*_{0} is the impedance between the given node pair with the amplifier’s dependent source set to zero (*a _{v}* → 0 for op amps,

*g*→ 0 for transistors); moreover,

_{m}*T*

_{RR}_{(sc)}and

*T*

_{RR}_{(oc)}are the return ratios with the node pair

*short circuited*and

*open circuited*, respectively. In the case of a purely series-type port we have

*T*

_{RR}_{(oc)}= 0, and in the case of a purely shunt-type port we have

*T*

_{RR}_{(sc)}= 0. As we know, RRA is generally quicker than TPA because it does not require any topology-dependent circuit manipulations [2].

Impedance transformations can be quite dramatic at low frequencies, where the loop gain is usually very high. However, as the open-loop gain rolls off with frequency, so does the loop gain, indicating that what’s high is bound to drop with frequency, and what’s low is bound to rise with frequency, at least over a certain frequency range. Put another way, series-type impedances exhibit *capacitive* behavior, and shunt-type impedances exhibit *inductive* behavior.

The drop of a series-type impedance may not necessarily be an issue so long as the impedance remains suitably high over the frequency range of interest. Shunt-type impedances, however, may pose problems, because when terminated on a capacitance, whether parasitic or intentional, the inductive component tends to *resonate* with the external capacitance, possibly leading to ringing and peaking, or even destabilizing the circuit [3].

It is precisely this destabilizing tendency that I want to address in the current blog. I will illustrate via the inverting amplifier of Figure 2, where *C _{L}* is the output load capacitance, and

*C*is the total capacitance of the inverting input pin (

_{n}*C*is the sum of the stray capacitances associated with the op amp’s input stage, the stray capacitances of

_{n}*R*

_{1}and

*R*

_{2}, and the stray capacitances of the wires [3]). For simplicity I will discuss the two cases separately, leaving their simultaneous treatment to my next blog.

**Figure 2.** **Circuit to investigate the destabilizing effect of capacitively-terminated shunt ports.**

**Next: Capacitive Loading**

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