Miller Compensation and the RHPZ

-October 28, 2014

For all its advantages, negative feedback poses a risk, namely, oscillation (this is why the engineering community didn’t immediately embrace this revolutionary concept when Harold Black conceived it, in 1928). To stave off possible oscillations, a circuit must be provided with a sufficient phase margin φm. As depicted in Figure 9 of Ref. [1] for the case of a second-order system, the frequency response exhibits peaking for φm < 65°, and the transient response exhibits ringing for φm < 75°.  The smaller φm, the larger the amount of peaking and ringing.  For φm < 0° the circuit becomes oscillatory.  As an example, the feedback-bias transistor of Figure 2 of Ref. [1] has φm ≅ 86°, which is considered to be a good phase margin.

If a circuit does not enjoy enough phase margin, we need to reshape the frequency profile of its loop gain T(jf) in such a way as to raise φm to the desired level - a task known as frequency compensation. Depending on the application, popular phase-margin specifications are φm = 90°, 75°, 60°, and at times even 45°.  Since T(jf) = α(jf)xβ(jf), reshaping T(jf) requires reshaping the open-loop gain α(jf), or the feedback factor β(jf), or both.  In Ref. [2] we have taken the viewpoint of the IC user, who stabilizes a circuit by reshaping β(jf) for a given a(jf).  In the current blog we take the viewpoint of the IC designer, who reshapes a(jf) so as to ensure a prescribed φm for a given range of βs, typically for frequency-independent feedback with β < βmax.  Most op amps are compensated for βmax = 1, in which case T(jf) = α(jf)x1 = α(jf), so T(jf) now coincides with α(jf).  However, some op amps are compensated for βmax < 1, such as βmax = 0.2, this being the reason why they are said to be decompensated


Based on the transistor example of Figure 2 of Ref. [1], it is reasonable to assume that the response of each gain stage of an amplifier be dominated by a single pole, which can erode φm by as much as 90°.  Consequently, in, say, a two-stage amplifier, we may have a phase erosion by as much as 2 x 90° = 180°, making φm approach zero.  (In practice, because of additional high-frequency poles, φm may actually be even negative).  The most popular frequency-compensation technique is to lower one of the poles so as to make it dominate α(jf) over the entire frequency range of interest.  This form of compensation aims toward the idealized response depicted in Figure 1a, which we express mathematically as

where a0 is the dc gain and f1 is the pole frequency.  We observe that at high frequencies we have

 


Figure 1 (a) Single-pole response, and (b) two-pole response with a dominant pole frequency at f1 and a second pole frequency at locations giving, respectively, φm = 45°, 60°, and 75°. 


indicating that above f1, the gain-bandwidth product, defined as GBP = |a|xf, is

Moreover, the frequency ft at which |a| drops to unity, or 0 dB, is such that GBP = 1 x ft, or

Since we are assuming β = 1, we rephrase the phase margin as

In Figure 1a we have ph a(jft) = –90°, so φm = 180 – 90 = 90°. 

As it approaches the transition frequency ft, the response of a real-life op amp deviates somewhat from the idealized response of Figure 1a due to the presence of additional high-frequency poles (and possibly zeros). This is exemplified by the popular 741 op amp of Figure 2, which has GBP = 1 MHz, but for which cursor measurements give ft = 0.888 MHz (< GBP), and φt = ph a(jft) = –117° (< –90°), so φm = 180 – 117 = 63° (< 90°).  Assuming that the additional phase shift of –27° can be ascribed to a single high-frequency pole f2, we readily calculate f2 by imposing –27° = –tan–1(0.888/f2), which gives f2 = 1.743 MHz.  As we proceed, we will find it useful to know the position of this second pole for a given φm, in the manner depicted in Figure 2b.  The results are summarized as follows:


Figure 2 Using PSpice to plot the open-loop gain of the 741 op amp (VCC = –VEE = 10 V.)

It is also useful to keep in mind the following:


Miller Compensation

A pole is made dominant by deliberately adding capacitance to the internal node responsible for that pole.  Anticipating a low-valued pole frequency (such as 5 Hz for the 741), we expect the added capacitance to be fairly large.  Miller compensation exploits the Miller effect (see the Appendix) to simulate a large capacitance using a physically small capacitor Cc that can easily be fabricated on chip without wasting precious area.  This form of compensation is depicted in Figure 3 for the case of a capacitively loaded CMOS amplifier.  Figure 4 shows the high-frequency model, which includes also the transistors’ stray capacitances C1 through C4.  These capacitances are usually much smaller than Cc and CL, so to help develop a basic feel for circuit operation, let us ignore C1 through C4 for the time being.

Figure 3 AC model of a Miller-compensated, capacitively-loaded two-stage CMOS amplifier.

We observe that the nodes labeled as V1 and Vo establish two poles in the left half-plane (LHPPs). Moreover, as discussed in the Appendix, the transmission capacitance Cc establishes a zero in the right half-plane (RHPZ). We therefore anticipate a gain expression of the type

where a0 is the dc gain, f0 is the RHP zero frequency, and f1 and f2 are the LHP pole frequencies.


Figure 4
High-frequency model of the two-stage amplifier of Figure 3.

Let us use physical insight to develop expressions for each parameter. At dc all capacitors act as open circuits, so we have two inverting stages with dc gains of a10 = –gm1R1 and a20 = –gm2R2, respectively. The overall dc gain is thus a0 = a10 x a20, or

Adapting Equation (A2) of the Appendix, we have

Based on Equation (A1) of the Appendix, the pole frequency associated with node V1 is

With reference to Figure 3, we can say that at sufficiently high frequencies, Cc forms an ac short between M2’s drain and source terminals, making M2 operate in the diode mode, where it exhibits a resistance of about 1/gm2. Together with CL, this resistance forms the second pole, whose frequency is thus

The magnitude and phase angle of the gain of Equation (6) are, respectively,



Note that unlike a LHPZ, a RHPZ contributes phase lag, just like the LHPPs f1 and f2Figure 5 shows a possible frequency profile of the gain of Equation (6).  Using Equations (7) and (9) we have, for gm2R2 >> 1,


Figure 5 Possible Bode plot for the circuit of Figure 4.

The Much Dreaded RHPZ

Depending on the location of f0 relative to that of f2, we have some interesting situations.  To help better visualize things, use the following insightful expressions, which you can easily derive from the above equations,

Consider first the case gm2 >> gm1, which is typical of bipolar op amps (for instance, in the 741 op amp, gm2 is more than 30 times greater than gm1).  Anticipating ft ~ GBP, we expect f0 (>> ft) to have negligible effect upon ph a(jft).  So, if you want to design for, say, φm = 75° for a given CL, ignore f0 and adapt Equation (5a) to impose

Then, once you know GBP, use Equation (12) to calculate the required compensation capacitance as

What if the condition gm2 >> gm1 does not hold? This is the case of two-stage CMOS op amps, which typically have gm2 ≅ 2gm1. The RHPZ is now close enough to GBP to have an appreciable impact upon φm. Assuming again ft ~ GBP, the RHPZ will erode φm by tan–1(ft/f0) ≅ tan–1(1/2) = 26.5°.

A rather interesting phenomenon occurs if we let Cc = CL to make f0 coincide with f2, by Equation (13b). Then, the numerator term involving f0 in Equation (11a) will cancel out the denominator term involving f2, leaving only the term involving f1, thus giving the false impression of a single-pole system. However, looking at Equation (11b), we note that the combined phase delay due to f0 and f2 is twice that due to f2 alone!

Needless to say, unless it is sufficiently high, a RHPZ is very unwelcome, and the best way to deal with it is to eliminate it altogether. But how? To answer, we need to take a closer look at what is going on physically in the circuit. To this end, consider the current through Cc, assumed to flow from left to right in Figure 6. This current is given by (V1Vo)/(1/j2πfCc), or (V1Vo)x(j2πfCc), and as such it can be decomposed into a forward component If(jf) and a reverse component Ir(jf),

 

            If(jf) = j2π fCcV1                                Ir(jf) = j2π fCcVo           

The reverse component Ir is responsible for making Cc appear magnified by the Miller effect when



Figure 6 Decomposing the current through Cc into a forward and a reverse component.

reflected to node V1, so it is desirable because it helps establish the dominant pole. By contrast, the forward component If is undesirable because it is responsible for the RHP transmission zero. The best way to cope with this zero is to block the transmission of If to the output node Vo while retaining the current Ir into node V1.  Good candidates for this task are voltage/current buffers because of their inherent unidirectionality.

Figure 7 Using the unity-gain voltage buffer E to block transmission to the output node Vo.


The scheme of Figure 7 interposes a unity-gain voltage buffer (E) between Cc and node Vo (input from Vo, output to Cc), to supply Cc (and, hence, node V1) with Ir while shunting If to ac ground. An alternative is to interpose a unity-gain current buffer between node V1 and Cc (input from Cc, output to V1), which will again supply V1 with Ir while inhibiting If with its high output impedance. (In a CMOS op amp, the buffers are implemented, respectively, with a common-drain and a common-gate MOSFET). With forward transmission out of the way, we are essentially left with a two-pole system that we can stabilize in the manner exemplified by Equation (13). Thus, for φm = 75°, we calculate


Figure 8 Bode plots for the circuit of Figure 7 (#1 traces). Also shown are the plots in the absence of the voltage buffer E, that is, with node Vo tied directly to Cc (#2 traces).

Figure 9 A frequency-compensated two-stage CMOS op amp [3].


(If a different φm is desired, replace the 3.605 term in accordance with Equation (5); for instance, for φm = 60°, replace 3.605 with 1.5 and get Cc = 0.75 pF.)  The results of the simulation, shown in Figure 8 (#1 traces) reveal ft = 42 MHz and φt = –104.6°, so φm = 75.4°.  Without the buffer (#2 traces) the circuit gives ft = 47 MHz and φt = –134°, so φm = 46°, which would result in appreciable peaking and ringing. 


A popular alternative for dealing with the RHPZ is to place a resistance Rc in series with Cc, as discussed in the Appendix.  This is exemplified [3] in Figure 9 for the case of a two-stage CMOS op amp. Here, M1 through M4 form the first stage, and M5 forms the second stage, with gm5 = 0.9344 mA/V.



Figure 10 Bode plots for the circuit of Fig. 9 (#1 traces). Also shown are the cases Rc = 0 (#2 traces) and Rc = Cc = 0 (#3 traces).

Letting Rc = 1/gm5 = 1/0.9344 = 1.07 kΩ yields f0 → ∞, after which we can tweak with the calculated value of Cc until we get the desired φm.  The results, shown in Figure 10 (#1 traces) reveal GBP = 33 MHz, ft = 32.0 MHz, and φt = –105°, so φm = 75°.  With Rc = 0 (#2 traces) the circuit would give ft = 35.1 MHz and φt = –131.4°, or φm = 48.6°, indicating that the presence of Rc improves φm by 75 – 48.6 = 26.4°.

Figure 10 shows also the uncompensated response (#3 traces), which has ft = 361 MHz and φt = –183.6°, so φm = –3.6°! This response is due to the internal parasitics of the various transistors, which SPICE calculates automatically based on process parameters and device geometries. It is apparent that the compensated response is dominated by Cc and CL, thus justifying our earlier decision to ignore the parasitics.  In practice, one would first ignore the parasitics to come up with an initial estimate for Cc, and then tweak with the value of Cc (and possibly Rc) until the desired phase margin is achieved.  We also see a notorious consequence of frequency compensation, namely, a drastic reduction of the open-loop bandwidth compared to the uncompensated case.  But, this is the price we must pay for stability!

Appendix

Placing a capacitor Cc in the feedback path of an inverting amplifier has two effects: (1) an increase in the apparent value of Cc as seen from the input (Miller effect), and (2) the creation of a positive transmission zero (right half-plane zero or RHPZ).


Figure A1
Illustrating the Miller effect.

 

To illustrate the Miller effect, refer to Figure A1, where we find the input impedance Zeq as

 

indicating that Cc, as seen from the input node, appears magnified by the factor 1 + gm2R2. We justify this physically [3] as follows.  Consider first the circuit of Figure A2a, where we see that a 0-to-1 mV voltage change results in a charge transfer of ΔQV/Cc = (1 mV)/(1 pF) = 1 fC.  If we place the same Cc in the feedback path of an inverting amplifier with a gain of –99 V/V as in Fig. A2b, the voltage change experienced by Cc is now ΔV = [1 – (–99)] = 100 mV, so we now have ΔQ = ΔV/Cc = (100 mV)/(1 pF) = 100 fC. The change transfer in (b) is 100 times as large as in (a), indicating that seen from the input node, the capacitor-amplifier combination provides an equivalent capacitance 100 times as large, even though physically we still have only a 1-pF capacitor.  This capacitance transformation proves extremely useful when we need to establish a low-frequency pole using a large equivalent capacitance, and yet we want to retain the slew-rate advantages of using a small physical capacitor.


                                     (a)                                                          (b)

Figure A2 Intuitive illustration of the Miller effect. 



To illustrate the RHPZ, refer to Figure A3a, and consider the gain a2 = Vo/V1.  At low frequencies, where Cc acts as an open circuit, we have a2 → –gm2R2 (inverting amplifier).  At high frequencies, where Cc acts as a short, we have a2 → + 1 V/V (noninverting amplifier).  Clearly, a frequency f0 must exist at which gain changes polarity, or a2(jf0) = 0.  At this frequency we must have Vo(jf0) = 0, indicating that the current I sourced by Cc must be sunk entirely by the dependent source.  Imposing


and solving for s0, aptly called the s-plane zero, we obtain

indicating that this zero lies in the right-half of the complex plane, or RHPZ. (For a discussion of RHPZ peculiarities, see Ref. [4].)

Consider now the effect of placing a resistance Rc in series with Cc.  At the zero frequency we now have the situation depicted in A3b, where

so the s-plane zero is now

It is apparent that the presence of Rc gives us the ability to relocate s0 to a less harmful position of the frequency spectrum.  In particular, making Rc = 1/gm2 relocates s0 to infinity, and making Rc > 1/gm2 moves s0 to the left half-plane, thus turning the RHPZ into a LHPZ! The resistance Rc is usually the channel of a MOSFET biased in the ohmic region.

Figure A3 Circuits to investigate the RHP zero.

References

  1. Loop gain measurements
  2. Feedback and Impedances
  3. Analog Circuit Design: Discrete & Integrated, Sergio Franco, San Francisco State University
  4. Demystifying the RHPZ

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