Slope Compensation in PCMC DC-DC Converters

-March 25, 2015

Over the years I’ve run into a number of engineers who haven’t had the chance to fully master the concept of slope compensation in dc-dc converters.  I’ll try to clarify [1] this concept using the buck converter as a vehicle.   Figure 1 exemplifies the buck conversion principle.  The switch is toggled between the source VI and ground at a frequency of fS.  The corresponding period is TS = 1/fS, and the portion of TS during which the switch is in the up position is denoted as DTS, where D is the duty cycle (0 < D < 1).  A PSpice simulation of the circuit with fS = 100 kHz and D = 0.25 yields the waveforms of Figure 2.  Viewing the circuit as a low-pass filter, we note that after an initial transient, the circuit achieves a form of steady state during which VO settles around 3 V, though with a small amount of ripple.  If we raise D to 0.5, VO will settle around 6 V, and if we raise D to 0.75, VO will settle around 9 V. 


Figure 1
(a) Buck conversion principle (fS and D represent the frequency and duty cycle with which the switch is being toggled). (b) VO as a function of D.

In fact, it is easily seen that VO settles around the average of the square-wave denoted as vsw in Figure 1, which is

 

VO = DVI                                                                                (1)

 

Since 0 < D < 1, it is apparent that the circuit acts as a form of voltage divider, with Equation (1) holding regardless of the current demanded by the load RL.  Initially, a good portion of the inductor current goes into charging up C, but once the circuit reaches its steady state, the capacitor current will average to zero, so the average current IL supplied by the inductor will equal the average current IO demanded by the load.  In the above example, IL = IO = VO/RL = 3 A.


Figure 2
PSpice waveforms for the circuit of Figure 1 for the case fS = 100 kHz and D = 0.25.


The most popular application of the buck converter is the regulation of VO.  To regulate, the circuit of Figure 1 must include a controller to sense VO and to continuously adjust D so as to maintain VO at a prescribed value regardless of possible variations in VI.  Needless to say, the controller is a negative-feedback system.  The RLC values of Figure 1 were deliberately chosen for a critically damped transient, but the RLC circuit in use will not necessarily be critically damped, so it is the responsibility of the controller to provide sufficient phase margin to ensure adequate regulator dynamics. 


How does the controller adjust D?  There are two classes of controllers, voltage-mode and current-mode controllers.  The following discussion will address a popular subclass of the latter, namely, peak-current-mode control, or PCMC, an example of which is depicted in Figure 3.  To sense the inductor current iL, the circuit uses a small series resistor Rsense, whose voltage drop is then magnified by an amplifier having a gain of ai.  This amplifier converts iL to the voltage RiiL, where

 

is the overall gain of the current-to-voltage conversion, in V/A, or ohms.  To sense the output voltage VO, the circuit uses the voltage divider R1-R2 to generate the voltage βVO, with


Figure 3
Circuit schematic of a PCMC buck converter without slope compensation.

   

Central to the system is the error amplifier EA, a high-gain amplifier that compares βVO against a reference voltage VREF and outputs whatever voltage vEA it takes to make their difference approach zero, thus giving

Once it reaches its steady state, the circuit operates as follows:

A cycle initiates when a clock pulse sets the flip-flop.  This closes the Mp switch to make vSW = VI.  During this portion of the cycle, denoted as DTS in Figure 4, the inductor current iL ramps up with a slope of Sn governed by the iL-vL inductor law, or Sn = diL/dt = vL/L.  During this time we have vL = VIVO, so


 


Figure 4
Steady-state waveforms in peak-current-mode control (PCMC).

     

Turning back to Figure 3, we observe that the CMP comparator continuously compares the voltage RiiL against the voltage vEA, and that as soon as RiiL reaches vEA, the CMP trips to reset the flip-flop.  Dividing both sides by Ri, this is equivalent to saying that the CMP trips as soon as iL reaches the value

 

This allows us to visualize a cycle exclusively in terms of currents as in Figure 4.  Now, resetting the flip-flop opens the Mp switch while closing the Mn switch to make vSW = 0.  During the remainder of the cycle, denoted as (1 – D)TS, we have vL = 0 – VO, so iL ramps down with a slope of Sf such that

A new cycle begins with the arrival of the next clock pulse.

   

Two Flaws of Uncompensated PCMC

 

As is, the circuit of Figure 3 suffers from two flaws.  The first flaw is depicted in Figure 5 for the case of a converter designed to regulate VO at 3.0 V (for simplicity, a cycle is assumed to start at t = 0).  Figure 4a shows the steady-state inductor current iL and its average IL for the case VI = 9 V, corresponding to a duty cycle of D = 3/9 = 1/3.  Suppose now VI drops to 4.5 V, corresponding to a duty cycle of D = 3/4.5 = 2/3.  Assuming vEA hasn’t had time to change appreciably, the average inductor current IL will rise as in Figure 5b.  This is so because while the down-slope Sf remains constant at –3/L, the up-slope Sn decreases from (9 – 3)/L to (4.5 – 3)/L, that is, from 6/L to 1.5/L.  With an increased IL, VO will also tend to increase, indicating poor regulation.

Figure 5 The inductor current of the circuit of Figure 3 for two different duty cycles.


The second flaw is a form of instability known as sub-harmonic oscillation, which arises for D > 0.5.  Figure 6 shows how an inductor current perturbation il(0) at the beginning of a cycle evolves into the perturbation il(TS) at the end of the cycle.  (A perturbation might be due, for instance, to a misfiring of the comparator in the course of the previous cycle.)  Using simple geometry we can write il(0)/Δt = Sn and il(TS)/Δt = Sf.  Eliminating Δt gives


indicating that (a) the polarity of il(TS) is opposite to that of il(0), and (b) for D < 0.5 its magnitude will decrease to die out after a sufficient number of cycles, but for D > 0.5 it will tend to increase from one cycle to the next, leading to the aforementioned sub-harmonic instability.   

 


Figure 6
Illustrating sub-harmonic oscillation for D > 0.5.


Slope Compensation

 

Looking back at Figure 5, we observe that if we want Figure 5b to retain the same IL value as Figure 5a, we need to reduce the iEA value of Figure 5b so as to “push down” the iL waveform till the respective ILs align.  By how much do we need to reduce iEA?  To answer, let us draw the desired iL waveforms for three different values of D.  As depicted in Figure 7, top, we start out by drawing the down-ramps for iL, all vertically centered about identical ILs, and all with the same slope of Sf = -VO/L.  Next, we complete the iL waveforms by drawing the up-ramps, as shown in Figure 7, bottom.  Finally, we superimpose the three figures as in Figure 8, and observe that the locus of the peaks defines a ramp with a slope of Sf/2 = –VO/2L.

   


Figure 7
Constructing the compensated iL waveforms for D = 0.25, 0.5, and 0.75.

       


Figure 8
The locus of the peaks of Figure 7 is a ramp with a slope of Sf/2.



Figure 9
Incorporating slope compensation in the PCMC buck converter of Figure 3.

   

This shows precisely by how we must reduce iEA, hence the designation slope compensation

Figure 9 shows one way of modifying the circuit of Figure 3 so as to achieve slope compensation. The circuit now includes a saw-tooth generator operating at a frequency of fS, whose output vRAMP is then subtracted from vEA to produce the desired locus of peak values for iL.  With slope compensation, the waveforms of Figure 5 change as depicted in Figure 10, where iEA(comp) = (vEAvRAMP)/Ri.  

         


Figure 10
The inductor current of the circuit of Figure 9 for two different duty cycles.

As an added bonus, slope compensation also eliminates sub-harmonic oscillation, as depicted in Figure 11.  Using graphical inspection, we observe that a beginning-of-cycle disturbance il(0) will result in an end-of-cycle disturbance il(TS) of lesser magnitude, even though D > 0.5 (in fact, you can convince yourself that this holds for any value of D, 0 < D < 1).  It is the case to say that with slope compensation we are in effect killing two birds with one slope – ops stone.The error amplifier EA, shown in Figure 9 as a mere triangle, serves two important functions: (a) to drive its inverting input voltage as close as necessary to the non-inverting one so as to approximate Eq. (4), and (b) to provide a frequency profile suitable to ensure a prescribed phase margin for the whole system.  Not at all an ordinary amplifier, which can easily form the body of a future blog on stability analysis and error-amplifier design.      

 


Figure 11
Slope compensation prevents sub-harmonic oscillation regardless of D.

   

References

[1] Design with Operational Amplifiers and Analog Integrated Circuits, Sergio Franco

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