# Slope Compensation in PCMC DC-DC Converters

Over the years I’ve run into a number of engineers who haven’t had the chance to fully master the concept of slope compensation in dc-dc converters. I’ll try to clarify [1] this concept using the buck converter as a vehicle. Figure 1 exemplifies the buck conversion principle. The switch is toggled

**Figure 1 ****- ( a) Buck conversion principle (f_{S} and D represent the frequency and duty cycle with which the switch is being toggled). (b) V_{O} as a function of D.**

between the source *V _{I}* and ground at a frequency of

*f*. The corresponding period is

_{S}*T*= 1/

_{S}*f*, and the

_{S}portion of* T _{S}* during which the switch is in the

*up*position is denoted as

*DT*, where

_{S}*D*is the

*duty cycle*(0 <

*D*< 1). A PSpice simulation of the circuit with

*f*= 100 kHz and

_{S}*D*= 0.25 yields the waveforms of Figure 2. Viewing the circuit as a

*low-pass filter*, we note that after an initial transient, the circuit achieves a form of

*steady state*during which

*V*settles around 3 V, though with a small amount of ripple. If we raise

_{O}*D*to 0.5,

*V*will settle around 6 V, and if we raise

_{O}*D*to 0.75,

*V*will settle around 9 V. In fact, it is

_{O}

**Figure 2 ****- PSpice waveforms for the circuit of Figure 1 for the case f_{S} = 100 kHz and D = 0.25.**

easily seen that *V _{O}* settles around the

*average*of the square-wave denoted as

*v*in Figure 1, which is

_{sw}

*V _{O}* =

*DV*(1)

_{I}

Since 0 < *D* < 1, it is apparent that the circuit acts as a form of *voltage divider*, with Equation (1) holding regardless of the current demanded by the load *R _{L}*. Initially, a good portion of the inductor current goes into charging up

*C*, but once the circuit reaches its steady state, the capacitor current will average to zero, so the average current

*I*supplied by the inductor will equal the average current

_{L}*I*demanded by the load. In the above example,

_{O}*I*=

_{L}*I*=

_{O}*V*= 3 A.

_{O}/R_{L} The most popular application of the buck converter is the regulation of *V _{O}*. To regulate, the circuit of Figure 1 must include a

*controller*to sense

*V*and to continuously adjust

_{O}*D*so as to maintain

*V*at a prescribed value regardless of possible variations in

_{O}*V*. Needless to say, the controller is a negative-feedback system. The

_{I}*RLC*values of Figure 1 were deliberately chosen for a

*critically damped*transient, but the

*RLC*circuit in use will not necessarily be critically damped, so it is the responsibility of the controller to provide sufficient phase margin to ensure adequate regulator dynamics.

How does the controller adjust *D*? There are two classes of controllers, *voltage-mode* and *current-mode* controllers. The following discussion will address a popular subclass of the latter, namely, *peak-current-mode control*, or PCMC, an example of which is depicted in Figure 3. To sense the inductor current *i _{L}*, the circuit uses a small series resistor

*R*

_{sense}, whose voltage drop is then magnified by an amplifier having a gain of

*a*. This amplifier converts

_{i}*i*to the voltage

_{L}*R*, where

_{i}i_{L}

is the overall gain of the current-to-voltage conversion, in V/A, or ohms. To sense the output voltage *V _{O}*, the circuit uses the voltage divider

*R*

_{1}-

*R*

_{2}to generate the voltage

*β*

*V*, with

_{O}

**Figure 3 **- **Circuit schematic of a PCMC buck converter without slope compensation.**

Central to the system is the *error amplifier* *EA*, a high-gain amplifier that compares *β**V _{O}* against a reference voltage

*V*

_{REF}and outputs whatever voltage

*v*it takes to make their difference approach zero, thus giving

_{EA}

Once it reaches its steady state, the circuit operates as follows:

A cycle initiates when a clock pulse sets the flip-flop. This closes the *M _{p}* switch to make

*v*=

_{SW}*V*. During this portion of the cycle, denoted as

_{I}*DT*in Figure 4, the inductor current

_{S}*i*ramps up with a slope of

_{L}*S*governed by the

_{n}*i*-

_{L}*v*inductor law, or

_{L}*S*=

_{n}*di*/

_{L}*dt*=

*v*/

_{L}*L*. During this time we have

*v*=

_{L}*V*–

_{I}*V*, so

_{O}

**Figure 4 **- **Steady-state waveforms in peak-current-mode control (PCMC).**

Turning back to Figure 3, we observe that the *CMP* comparator continuously compares the voltage *R _{i}i_{L}* against the voltage

*v*, and that as soon as

_{EA}*R*reaches

_{i}i_{L}*v*, the

_{EA}*CMP*trips to reset the flip-flop. Dividing both sides by

*R*, this is equivalent to saying that the

_{i}*CMP*trips as soon as

*i*reaches the value

_{L}* *

This allows us to visualize a cycle* *exclusively in terms of currents as in Figure 4. Now, resetting the flip-flop opens the *M _{p}* switch while closing the

*M*switch to make

_{n}*v*= 0. During the remainder of the cycle, denoted as (1 –

_{SW}*D*)

*T*, we have

_{S}*v*= 0 –

_{L}*V*, so

_{O}*i*ramps down with a slope of

_{L}*S*such that

_{f}

A new cycle begins with the arrival of the next clock pulse.

**Two Flaws of Uncompensated PCMC**

As is, the circuit of Figure 3 suffers from two flaws. The first flaw is depicted in Figure 5 for the case of a

**Figure 5 **-** The inductor current of the circuit of Figure 3 for two different duty cycles.**

converter designed to regulate *V _{O}* at 3.0 V (for simplicity, a cycle is assumed to start at

*t*= 0). Figure 4

*a*shows the steady-state inductor current

*i*and its average

_{L}*I*for the case

_{L}*V*= 9 V, corresponding to a duty cycle of

_{I}*D*= 3/9 = 1/3. Suppose now

*V*drops to 4.5 V, corresponding to a duty cycle of

_{I}*D*= 3/4.5 = 2/3. Assuming

*v*hasn’t had time to change appreciably, the average inductor current

_{EA}*I*will rise as in Figure 5

_{L}*b*. This is so because while the down-slope

*S*remains constant at –3/

_{f}*L*, the up-slope

*S*decreases from (9 – 3)/

_{n}*L*to (4.5 – 3)/

*L*, that is, from 6/

*L*to 1.5/

*L*. With an increased

*I*,

_{L}*V*will also tend to increase, indicating poor regulation.

_{O} The second flaw is a form of instability known as *sub-harmonic oscillation*, which arises for *D* > 0.5. Figure 6 shows how an inductor current perturbation *i _{l}*(0) at the beginning of a cycle evolves into the perturbation

*i*(

_{l}*T*) at the end of the cycle. (A perturbation might be due, for instance, to a misfiring of the comparator in the course of the previous cycle.) Using simple geometry we can write

_{S}*i*(0)/Δ

_{l}*t*=

*S*and

_{n}*i*(

_{l}*T*)/Δ

_{S}*t*=

*S*. Eliminating Δ

_{f}*t*gives

** **

** **

**FIGURE 6** **– Illustrating sub-harmonic oscillation for D > 0.5.**

indicating that (

*a*) the polarity of

*i*(

_{l}*T*) is

_{S}*opposite*to that of

*i*(0), and (

_{l}*b*) for

*D*< 0.5 its magnitude will decrease to die out after a sufficient number of cycles, but for

*D*> 0.5 it will tend to increase from one cycle to the next, leading to the aforementioned sub-harmonic instability.

**Slope Compensation**

Looking back at Figure 5, we observe that if we want Figure 5*b* to retain the same *I _{L}* value as Figure 5

*a*, we need to reduce the

*i*value of Figure 5

_{EA}*b*so as to “push down” the

*i*waveform till the respective

_{L}*I*s align. By how much do we need to reduce

_{L}*i*? To answer, let us draw the desired

_{EA}*i*waveforms for three different values of

_{L}*D*. As depicted in Figure 7, top, we start out by drawing the down-ramps for

*i*, all vertically

_{L}

**Figure 7 **-** Constructing the compensated i_{L} waveforms for D = 0.25, 0.5, and 0.75.**

centered about identical *I _{L}*s, and all with the same slope of

*S*= -

_{f}*V*/

_{O}*L*. Next, we complete the

*i*waveforms by drawing the up-ramps, as shown in Figure 7, bottom. Finally, we superimpose the three figures as in Figure 8, and observe that the

_{L}*locus*of the peaks defines a ramp with a slope of

*S*/2 = –

_{f}*V*/2

_{O}*L*.

**Figure 8 **- **The locus of the peaks of Figure 7 is a ramp with a slope of S_{f}/2.**

**Figure 9 **- **Incorporating slope compensation in the PCMC buck converter of Figure 3.**

This shows precisely by how we must reduce *i _{EA}*, hence the designation

*slope compensation*.

Figure 9 shows one way of modifying the circuit of Figure 3 so as to achieve slope compensation. The circuit now includes a saw-tooth generator operating at a frequency of *f _{S}*, whose output

*v*is then subtracted from

_{RAMP}*v*to produce the desired locus of peak values for

_{EA}*i*. With slope compensation, the waveforms of Figure 5 change as depicted in Fig. 10, where

_{L}*i*

_{EA}_{(comp)}= (

*v*–

_{EA}*v*)/

_{RAMP}*R*.

_{i}** **

**Figure 10 **-** The inductor current of the circuit of Figure 9 for two different duty cycles.**

As an added bonus, slope compensation also eliminates sub-harmonic oscillation, as depicted in Figure 11. Using graphical inspection, we observe that a beginning-of-cycle disturbance *i _{l}*(0) will result in

**Figure 11 ****- Slope compensation prevents sub-harmonic oscillation regardless of D.**

an end-of-cycle disturbance *i _{l}*(

*T*) of

_{S}*lesser*magnitude, even though

*D*> 0.5 (in fact, you can convince yourself that this holds for any value of

*D*, 0 <

*D*< 1). It is the case to say that with slope compensation we are in effect killing two birds with one slope – ops stone.

The error amplifier *EA*, shown in Figure 9 as a mere triangle, serves two important functions: (*a*) to drive its inverting input voltage as close as necessary to the non-inverting one so as to approximate Eq. (4), and (*b*) to provide a frequency profile suitable to ensure a prescribed phase margin for the whole system. Not at all an ordinary amplifier, which can easily form the body of a future blog on stability analysis and error-amplifier design.

**References**

[1] Design with Operational Amplifiers and Analog Integrated Circuits by Sergio Franco

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