External components improve SAR-ADC accuracy

It is tempting to use an op amp to directly drive the input of a SAR (successive-approximation-register) ADC. Unfortunately, this configuration can limit circuit performance. An external RC (resistor-capacitor) network better isolates the converter from the driver amplifier and allows greater flexibility in op-amp selection. Getting the best performance from a SAR ADC may be more important than you think. Even if you convert signals that are well below the frequency limitations of the converter and amplifier, you can’t ignore the dynamic characteristics of the SAR ADC’s input structure.

Figure 1 shows a single-supply combination SAR-ADC/op-amp circuit. This circuit places the op amp in an inverting-gain configuration. IC₁ is a unity-gain-stable, single-supply CMOS op amp with a gain-bandwidth product of 5 MHz. The single-supply configuration avoids the effect of the amplifier-input limitations, such as a limited input range and input common-mode-crossover distortion. The designer of this circuit uses the ADC-reference output to bias the amplifier’s noninverting input as well as the negative input of the ADC, thus keeping the op-amp operation between the supply rails. IC₂ is a 12-bit, 500k-sample/sec SAR ADC.

In Figure 1, the circuit appears to be functional; the op amp’s low-impedance output drives the SAR ADC. Figure 2 shows the FFT-test results for this circuit, with a 15-kHz op-amp-input signal. In Figure 2a, the SAR ADC’s acquisition time equals 265 nsec. In Figure 2b, the acquisition time is 560 nsec. These acquisition times extend neither the op amp nor the ADC beyond its specified performance limits.

The measurement results show that the length of the acquisition time affects the performance; increasing the acquisition time from 250 to 560 nsec improves the performance, although increasing the acquisition time also slightly increases the total throughput time. With the longer acquisition time, the SNR (signal-to-noise ratio) increases from 70.8 to 71.5 dB and the THD (total harmonic distortion) decreases from –71.4 to –78.6 dB (Reference 1).

Standard SAR-ADC model

A capacitive SAR ADC’s input stage contains a capacitive-charge-redistribution network (Figure 3 and Reference 2 and Reference 3). In Figure 3, V_SH0 is the initial voltage across the sampling capacitor, C_SH. Depending on the converter’s input structure, this voltage can equal the input during the previous conversion, ground, or V_REF. Opening S₂ and closing S₁ cause signal acquisition. When S₁ closes, the voltage across the sampling capacitor, C_SH, changes to V_IN. Charge from the voltage source, V_IN, passes through the sampling-switch path of S₁ and R_S1 onto C_SH. As the charge redistributes itself, the charge previously on C_SH changes so that V_CSH equals V_IN (Figure 4).

If you consider only the ADC input, the ADC’s bandwidth depends on the internal sampling capacitor, C_SH, and the switch resistance, R_S1. From the time constant, τ=R_S1×C_SH, you can derive the settling time of this one-pole system. The minimum acquisition time for the SAR converter is the time required for the sampling mechanism to capture the input voltage. The acquisition time begins after the issuance of the sample command and the charging of the hold capacitor, C_SH.

You can use the following equations to determine the settling time for the network in Figure 3.

where V_CSH(t) is voltage versus time across the sampling capacitor, C_SH; V_CSH(t₀) is voltage across the sampling capacitor, C_SH, at the start of the acquisition time; V_IN is the ADC’s input voltage; τ is the acquisition-time constant, equal to R_S1×C_SH; and t is a time variable in seconds.

If you want the error not to exceed ½ LSB, the time at which the voltage on the sampling capacitor, C_SH, approaches within ½ LSB of the input voltage establishes the acquisition time.

where V_CSH(t_AQ) is voltage across the sampling capacitor, C_SH, at the end of the sampling period, and t_AQ is the acquisition time, or the amount of time from the beginning of the sampling period (t₀) to the end of the sampling period. Further,

where FSR is the input full-scale range of the N-bit converter.

If you change V_CSH(t) to V_CSH(t_AQ) and V_CSH(t₀) to V_SH0 and make Equation 1 and Equation 3 equal, you can derive the following equations:

You can calculate settling time as a function of the input-stage time constant and the time-constant multiplier, k, for a variety of ADC resolutions. Table 1 summarizes these calculations. You can use these calculations to evaluate the acquisition time of any SAR ADC. For the worst-case analysis (Equation 5 and Table 1), assume that V_SH0 equals 0V. Figure 5 shows the change of the initial charge of the Texas Instruments ADS8361, a 16-bit, 500k-sample/sec SAR ADC, as a function of the input-signal amplitude.

With the ADS8361, S₁’s closed-switch resistance, R_S1, is 20Ω. The ADS8361’s internal sampling capacitor, C_SH, is equal to 25 pF. From Figure 5, you can see that the sinusoidal input voltage frequency is much lower than the converter’s sampling frequency. If you measure lower input frequency signals, f_IN≤f_S/10, the calculation uses an initial voltage on V_SH0 equal to half of the full-scale range. On the other hand, if there is a front-end multiplexer, V_SH0 is 0V. For a 16-bit SAR ADC, the time-constant multiplier, k₁, for 1-LSB error equals 11.09. If you need ½-LSB error, k₂=11.78. The detailed discussion in Reference 4 explains how to determine the initial charge of the sampling capacitor in a capacitive SAR ADC.

A charge bank at the SAR-ADC input

Figure 6 illustrates a driving amplifier, followed by an RC pair that connects to the input of a SAR ADC. The capacitor, C_IN, acts as a charge bank that supplies ample charge to the SAR ADC’s internal capacitor array. Using the previous calculation for a 16-bit SAR ADC, the time constant, τ (τ=R_IN×C_IN), of the external RC filter in which k₂=t_AQ/τ is between 11 and 12. A k value of 11 or 12 does not degrade the performance of the signal chain. However, by fine-tuning the formulas, you can achieve optimum performance with lower k values.

Evaluating the charge-bank circuitry

In the circuit of Figure 6, the charge on C_IN follows the input voltage before and after the internal ADC sampling switch, S₁, closes. With this condition in mind, the timing evaluation ignores the influence of R_IN. Figure 7 shows the model of a new SAR-ADC system. In this system, capacitors C_IN and C_SH have different initial voltages. At the start of a conversion, the charge quickly redistributes between C_IN and C_SH through R_S1.

Figure 8 shows a simplified circuit for the capacitive input stage of the circuit in Figure 7. Before the input-signal acquisition, S₁ is open (Figure 8a). The input capacitor, C_IN, has an initial voltage of V_IN, and the voltage across the sampling capacitor, C_SH, equals V_SH0. S₁ closes at the start of signal acquisition (Figure 8b). The capacitor voltages, V_IN and V_CSH, become equal (Figure 8c) as the charge quickly redistributes between C_IN and C_SH.

The following equations calculate the charge on capacitors C_IN and C_SH:

After S₁ closes, the charge on C_IN and C_SH distributes between the capacitors. C_IN and C_SH combine into an equivalent capacitance, C_TOT (Figure 8b and Figure 8c). The effective capacitance and charge distribution are:

Using Equation 9 through Equation 12, you can calculate a new equivalent voltage on capacitors C_IN and C_SH:

Introducing the ratio C_IN/C_SH=α, Equation 13 transforms into:

Now, you can calculate the required time constant of the input RC for the circuit in Figure 6.

where V_TOT(t₀) is the voltage across the capacitor, C_TOT, at the end of the sampling period. By changing V_TOT(t) to V_TOT(t₀) and making Equation 15 and Equation 17 equal, you obtain:

Now, you can define a new way of calculating the time-constant multiplier, k₃, using Equation 14 and Equation 19.

Equation 20 shows that k3 is a function of not only the initial charge, V_SH0, but also the external capacitor, C_IN. In the ADS8361, a 16-bit SAR ADC with a lower input-frequency signal of f_IN≤f_S/10, C_SH’s calculated initial charge, V_SH0, is half of the full-scale range. On the other hand, with the multiplexed signal at the input to the converter, you must use V_SH0=0V. With these assumptions, Equation 20 becomes:

Table 2 shows how k₃ changes as a function of C_IN and shows lower valued time-constant multipliers, k₃, for Figure 6’s 16-bit SAR ADC.

Test results

Figure 9 shows the results for the ADS8361, a 16-bit converter, tested in the configuration in Figure 6. The results show that the ADS8361 maintains good performance with SNR, SFDR (spurious-free dynamic range), and SINAD (signal, noise, and distortion) until k₃ becomes smaller than six. This result differs from the k₁-multiplier values of 11.1 and 11.78 that Table 1 generates. In Figure 9, the 16-bit ADS8361 SAR ADC operates at 200k samples/sec (t_AQ=3.4 μsec). The frequency of the input signal is 10 kHz. In Equation 20, the initial voltage on V_SH0 is equal to half the full-scale range. The value of the sampling capacitor, C_SH, is 25 pF, and the value of C_IN is 2.2 nF. With these assumptions, Equation 20 becomes:

Note that, in Figure 9, the improvement in SFDR is approximately 5 dB.

A little RC finesse helps

The following equations illustrate the key design guidelines for the SAR-ADC input circuits in Figure 6.

For multiplexed signals, this equation is:

And, for lower-input-frequency signals,

Acknowledgement

The authors wish to express special thanks to Art Kay, a senior applications engineer for Texas Instruments, for his help in developing the concept discussed herein.