External components improve SARADC accuracy
It is tempting to use an op amp to directly drive the input of a SAR (successiveapproximationregister) ADC. Unfortunately, this configuration can limit circuit performance. An external RC (resistorcapacitor) network better isolates the converter from the driver amplifier and allows greater flexibility in opamp selection. Getting the best performance from a SAR ADC may be more important than you think. Even if you convert signals that are well below the frequency limitations of the converter and amplifier, you can’t ignore the dynamic characteristics of the SAR ADC’s input structure.
Figure 1 shows a singlesupply combination SARADC/opamp circuit. This circuit places the op amp in an invertinggain configuration. IC_{1} is a unitygainstable, singlesupply CMOS op amp with a gainbandwidth product of 5 MHz. The singlesupply configuration avoids the effect of the amplifierinput limitations, such as a limited input range and input commonmodecrossover distortion. The designer of this circuit uses the ADCreference output to bias the amplifier’s noninverting input as well as the negative input of the ADC, thus keeping the opamp operation between the supply rails. IC_{2} is a 12bit, 500ksample/sec SAR ADC.
In Figure 1, the circuit appears to be functional; the op amp’s lowimpedance output drives the SAR ADC. Figure 2 shows the FFTtest results for this circuit, with a 15kHz opampinput signal. In Figure 2a, the SAR ADC’s acquisition time equals 265 nsec. In Figure 2b, the acquisition time is 560 nsec. These acquisition times extend neither the op amp nor the ADC beyond its specified performance limits.
The measurement results show that the length of the acquisition time affects the performance; increasing the acquisition time from 250 to 560 nsec improves the performance, although increasing the acquisition time also slightly increases the total throughput time. With the longer acquisition time, the SNR (signaltonoise ratio) increases from 70.8 to 71.5 dB and the THD (total harmonic distortion) decreases from –71.4 to –78.6 dB (Reference 1).
Standard SARADC model
A capacitive SAR ADC’s input stage contains a capacitivechargeredistribution network (Figure 3 and Reference 2 and Reference 3). In Figure 3, V_{SH0} is the initial voltage across the sampling capacitor, C_{SH}. Depending on the converter’s input structure, this voltage can equal the input during the previous conversion, ground, or V_{REF}. Opening S_{2} and closing S_{1} cause signal acquisition. When S_{1} closes, the voltage across the sampling capacitor, C_{SH}, changes to V_{IN}. Charge from the voltage source, V_{IN}, passes through the samplingswitch path of S_{1} and R_{S1} onto C_{SH}. As the charge redistributes itself, the charge previously on C_{SH} changes so that V_{CSH} equals V_{IN} (Figure 4).
If you consider only the ADC input, the ADC’s bandwidth depends on the internal sampling capacitor, C_{SH}, and the switch resistance, R_{S1}. From the time constant, τ=R_{S1}×C_{SH}, you can derive the settling time of this onepole system. The minimum acquisition time for the SAR converter is the time required for the sampling mechanism to capture the input voltage. The acquisition time begins after the issuance of the sample command and the charging of the hold capacitor, C_{SH}.
You can use the following equations to determine the settling time for the network in Figure 3.
where V_{CSH}(t) is voltage versus time across the sampling capacitor, C_{SH}; V_{CSH}(t_{0}) is voltage across the sampling capacitor, C_{SH}, at the start of the acquisition time; V_{IN} is the ADC’s input voltage; τ is the acquisitiontime constant, equal to R_{S1}×C_{SH}; and t is a time variable in seconds.
If you want the error not to exceed ½ LSB, the time at which the voltage on the sampling capacitor, C_{SH}, approaches within ½ LSB of the input voltage establishes the acquisition time.
where V_{CSH}(t_{AQ}) is voltage across the sampling capacitor, C_{SH}, at the end of the sampling period, and t_{AQ} is the acquisition time, or the amount of time from the beginning of the sampling period (t_{0}) to the end of the sampling period. Further,
where FSR is the input fullscale range of the Nbit converter.
If you change V_{CSH}(t) to V_{CSH}(t_{AQ}) and V_{CSH}(t_{0}) to V_{SH0} and make Equation 1 and Equation 3 equal, you can derive the following equations:
With the ADS8361, S_{1}’s closedswitch resistance, R_{S1}, is 20Ω. The ADS8361’s internal sampling capacitor, C_{SH}, is equal to 25 pF. From Figure 5, you can see that the sinusoidal input voltage frequency is much lower than the converter’s sampling frequency. If you measure lower input frequency signals, f_{IN}≤f_{S}/10, the calculation uses an initial voltage on V_{SH0} equal to half of the fullscale range. On the other hand, if there is a frontend multiplexer, V_{SH0} is 0V. For a 16bit SAR ADC, the timeconstant multiplier, k_{1}, for 1LSB error equals 11.09. If you need ½LSB error, k_{2}=11.78. The detailed discussion in Reference 4 explains how to determine the initial charge of the sampling capacitor in a capacitive SAR ADC.
A charge bank at the SARADC input
Figure 6 illustrates a driving amplifier, followed by an RC pair that connects to the input of a SAR ADC. The capacitor, C_{IN}, acts as a charge bank that supplies ample charge to the SAR ADC’s internal capacitor array. Using the previous calculation for a 16bit SAR ADC, the time constant, τ (τ=R_{IN}×C_{IN}), of the external RC filter in which k_{2}=t_{AQ}/τ is between 11 and 12. A k value of 11 or 12 does not degrade the performance of the signal chain. However, by finetuning the formulas, you can achieve optimum performance with lower k values.
Evaluating the chargebank circuitry
In the circuit of Figure 6, the charge on C_{IN} follows the input voltage before and after the internal ADC sampling switch, S_{1}, closes. With this condition in mind, the timing evaluation ignores the influence of R_{IN}. Figure 7 shows the model of a new SARADC system. In this system, capacitors C_{IN} and C_{SH} have different initial voltages. At the start of a conversion, the charge quickly redistributes between C_{IN} and C_{SH} through R_{S1}.
Figure 8 shows a simplified circuit for the capacitive input stage of the circuit in Figure 7. Before the inputsignal acquisition, S_{1} is open (Figure 8a). The input capacitor, C_{IN}, has an initial voltage of V_{IN}, and the voltage across the sampling capacitor, C_{SH}, equals V_{SH0}. S_{1} closes at the start of signal acquisition (Figure 8b). The capacitor voltages, V_{IN} and V_{CSH}, become equal (Figure 8c) as the charge quickly redistributes between C_{IN} and C_{SH}.
The following equations calculate the charge on capacitors C_{IN} and C_{SH}:
Again, to limit the error to ½ LSB, you must make the acquisition time long enough for the voltage on C_{TOT} to approach the input voltage within ½ LSB.
Test results
Figure 9 shows the results for the ADS8361, a 16bit converter, tested in the configuration in Figure 6. The results show that the ADS8361 maintains good performance with SNR, SFDR (spuriousfree dynamic range), and SINAD (signal, noise, and distortion) until k_{3} becomes smaller than six. This result differs from the k_{1}multiplier values of 11.1 and 11.78 that Table 1 generates. In Figure 9, the 16bit ADS8361 SAR ADC operates at 200k samples/sec (t_{AQ}=3.4 μsec). The frequency of the input signal is 10 kHz. In Equation 20, the initial voltage on V_{SH0} is equal to half the fullscale range. The value of the sampling capacitor, C_{SH}, is 25 pF, and the value of C_{IN} is 2.2 nF. With these assumptions, Equation 20 becomes:
Note that, in Figure 9, the improvement in SFDR is approximately 5 dB.
A little RC finesse helps
The following equations illustrate the key design guidelines for the SARADC input circuits in Figure 6.
To maximize the system’s SNR, the value of C_{IN} should be as large as possible with the op amp’s driving capability in mind. For preservation of the ADC’s THD, C_{IN} should be either a ceramic device with a chiponglass dielectric or a silvermica unit with ≤5% tolerance. The value of R_{IN} depends primarily on the acquisition time, the value of C_{IN}, and the op amp’s driving capability. R_{IN} isolates amplifier IC_{1} from load capacitor C_{IN}, which, for lownoise performance, should be a metalfilm device with ≤1% tolerance. The RC filter between the op amp and the SAR ADC may compromise the amplifier’s stability. Reference 5 provides more details on opamp selection and stability.
Acknowledgement
The authors wish to express special thanks to Art Kay, a senior applications engineer for Texas Instruments, for his help in developing the concept discussed herein.
References 

Complete the simulation of your ADC with IBIS
Simulating the frontend of your ADC
Painless reduction of analog filter noise
The inner workings of the threeopamp INA
Will the right voltage reference stand up?
Measuring amplifier DC offset voltage, PSRR, CMRR, and openloop gain
PCB signal coupling can be a problem
Phantom voltage dividers on your PCB
Accidental engineering: 10 mistakes turned into innovation
That 60Wequivalent LED: What you don’t know, and what no one will tell you…
6 famous people you may not know are engineers
DC distribution in your house and 42V cars
10 tips for a successful engineering resume
The 5 greatest engineers of all time
Higgs Pt. 9: What makes King Carl XVI Gustaf think it’s the Higgs Boson?
10 things you may not know about Tesla
Analog Fundamentals: Instrumentation for impedance measurement
Keeping smart lamps “EnergyEfficiency Smart”
7 cardinal sins of embedded software development
A tale of two science centres: Ontario Science Centre
Dave Freeman: Colleague and mentor
Review: The Aaronia BicoLOG 30100X and HyperLOG 7060 EMI antennas
Failed solder joint makes car clock go dark