Delta-sigma antialiasing filter with a mode-rejection circuit
The approach to the antialiasing-filter design for the delta-sigma data converter is significantly different from the approach you would use for a SAR (successive-approximation register) or pipeline (high-speed) converter. With SAR and pipeline converters, you have systems that evaluate one sample at a time. In both cases, the analog signal is “grabbed” and stored on the converter’s input capacitor array. These converters evaluate the stored signal and provide a digital representation of that single sample. With both devices, the target frequency for the multiorder, antialiasing filter is the converter’s Nyquist frequency.
The delta-sigma converter’s input modulator samples the input analog signal numerous times at a high sample rate (FS, Reference 1). The following sinc digital filter resamples and converts a group of these modulator samples to an output digital representation. The conversion process from the modulator’s string of samples to a 24-bit digital code is significantly slower (FD, Reference 1) than the sample rate of the delta sigma’s input structure. Consequently, the delta-sigma converter has two sample rates (FS, FD). The first-order antialiasing filter’s target frequency, however, is the output data rate, FD. You can find the fundamental antialiasing-filter design concepts for a delta-sigma converter in Reference 1.
Once you establish the target antialiasing frequency of FD, you can quickly define the theoretical design formulas, as Reference 2 discusses. The calculation for this theoretical evaluation takes into account resistor noise and converter bits. To determine the theoretical filter resistance (Figure 1), use the following equation:
where ER is the specified effective resolution from the ADC manufacturer’s data sheet, k is Boltzmann’s constant, and T is the temperature in Kelvin. To determine the theoretical filter capacitance, use the following equation:
Note that the circuits and the discussions presented in references 1 and 2 address only the reduction of differential noise, with no regard to the input impedance of the converter or common-mode noise.
In terms of the converter’s input impedance, the capacitors of a switched-capacitor-input, delta-sigma converter are continuously charged and discharged while measuring a voltage between AINP and AINN (Figure 2). These internal capacitors (CB, CA1, and CA2) are relatively small when compared with the external circuitry. Consequently, the average input impedance appears to be resistive. The converter’s capacitor values and modulator switching rate set this resistive value.
To measure the common-mode input impedance of the structure in Figure 2, tie AINP and AINN together and measure the average current that each pin consumes during conversion. To measure the differential input impedance, apply a differential signal to AINP and AINN and measure the average current that flows through the pin to VA. The common- and differential-mode resistance can range from hundreds of kilohms to hundreds of megohms. Those values depend on the circuitry following the input switching-capacitor structure inside the converter. The value of RFLT/2 must be at least 10 times lower than the converter’s input impedances.
The two common-mode capacitors, CCM_P and CCM_N, attenuate high-frequency common-mode noise. The differential capacitor should be at least an order of magnitude larger than the common-mode capacitors because mismatches in the common-mode capacitors cause differential noise.
If the input signal to any ADC contains frequencies greater than half the data rate, aliasing occurs. To prevent aliasing, bandlimit the input signals containing noise and interference components. The digital filters in delta-sigma converters provide some high-frequency noise attenuation, but the digital sinc filter cannot completely replace an antialiasing filter. When designing an input filter circuit, factor in the interaction between the filter network and the input impedance of the converter.