Insecure radio links and the end of Moore's Law discussed at DAC 2015
Are you concerned about all the insecure radio links out there? The DAC panel "The Researcher Who Cried Wolf" featured several speakers who presented some simultaneously entertaining and troubling stories about security problems of various sorts.
The first speaker, a self-described SDR (software-defined radio) evangelist, talked about all the open radio protocols out there, focusing on aircraft systems. He'd created some impressive animations of aircraft operations over both large geographic areas, and right down to simulated views out the windshield of aircraft at a nearby airport. He also showed demos of restaurant pager hacking and decoding of items like toll transponders and keyless entry. Fortunately, the talk was mostly of a cautionary nature. Use as much security as your app demands.
The second speaker, from TrapX Labs, covered IoT and related attacks. With even electric toothbrushes available that connect to your network, one realizes that the number of potential attack vectors is only going to keep increasing. He also pointed out the need to expect the unexpected, such as malware planted in a barcode reader! Malware has also been found in medical equipment like analyzers and image archive systems running older OSes. Finally, the Nest thermostat was discussed. Well designed from a security standpoint, it was still possible to plant modified units on store shelves which would allow access into the purchaser's network.
Next, the seemingly unlikely scenario of hardware trojans was discussed: the concept of modifying actual IC circuitry somewhere in the production process. The most undetectable scenario is changing doping of selected transistors to force various states and behaviours, the trick of course being it must be undetectable during test. A good example was that of a random number generator used for encryption, where the behaviour could be altered just enough to change the number distribution to be more predictable – something not likely to be detected in test. Shades of Enigma.
The Moore naysayers have been around for decades, predicting the demise of Moore's Law, but so far, they've been proven wrong. But these days, more and more people are agreeing the end is nigh. But not Intel's Vivek Singh. Despite oft-heard claims of flat or even increasing cost per transistor, Singh showed that transistor cost was actually continuing its exponential ride down to the zero limit. The 7nm node is already on track. His background is computational lithography, and he closed his talk with a pattern right out of a "magic eye" book. What was revealed when the pattern was "decoded"? A sketch of Gordon Moore, with the text,"Thank you Dr. Moore." Unfortunately, I was too slow on the shutter button, but it made it onto the DAC Blog:
News from the floor
ARM demonstrated its new Corelink and Coresight Creators, and Socrates DE tools, which greatly facilitate ARM SoC creation by eliminating tedious manual configuration of debug/trace, interconnect, and IP. It's a bit surprising these features didn't already exist, but ARM partners will doubtless be ecstatic.
A poster session concluded the day, with participants showing off interesting new work. Clock-crossing and electromigration were both well represented, as were many other lines of work. SystemC HLS was also seen, with Intel a strong proponent.
Sage Design Automaton's iDRM addresses the pain points re DRC creation and verification at advanced process nodes. The number and complexity of rules has arguably become unmanageable, and this looks like a solution.
Mentor's Veloce and Ansys' Power Artist now communicate directly instead of via interchange files in order to to speed up power simulation by several times. In addition, Mentor's hardware emulation platforms support from 250 million to 2 billion gates per chassis.
Open Silicon is an ASIC design house that also sells some FPGA/ASIC IP, including hybrid memory cube. I was impressed to learn that a small- to medium-sized IoT chip could be turned around in about six months.
FinFETs keep making news, with 10nm test wafers on display at DAC. At the now, dare I say it, routine 14nm node, Synopsys and ARM discussed a collaboration with Samsung's foundry to create a complex SoC using their 14LPP process and Synopsys' IC Compiler II and Lynx design system. The design team was then challenged to design a 16-core Cortex-A53 SoC, and took only four weeks to achieve a first-pass 1.5GHz design with only 18mW of leakage.
More from DAC:
- Google Smart Lens kicks off DAC 2015
- FPGAs, cloud design, and meta-tools at DAC 2015
- Bioresorbable electronics cap off DAC 2015
- First three rules of IoT security
- IoT security may lie in numbers
- Hearing aids hacked
- Moore’s Law creates new test product categories
- SSDs: mind-blowing Moore's law case studies