Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate
Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.
The latest announced capacity achievement comes from Seagate, who Tuesday unveiled the capability to squeeze 1 Tbyte on a single double-sided 3.5″ HDD platter. Granted, Seagate wasn’t the first to reach this per-platter threshold; Samsung broke similar news in early March. And since, as I mentioned a few weeks back, Seagate is in the process of acquiring Samsung, yesterday’s announcement may be little more than a regurgitation of the earlier release from the company in the process of being consumed. Nonetheless, let’s give credit where it’s due, to the companies’ engineers and materials scientists, and to their equivalents at the HDD controller chipset suppliers who are charged with translating this potential into high-volume production reality. And speaking of potential, my biggest question at the moment is when (or if?) Seagate will translate this storage achievement into a four-platter 4 TByte 3.5″ HDD, versus using it to platter count-reduce and therefore cost-reduce lower-capacity HDDs.
Speaking of high volume production, and of Intel, let’s now turn to Wednesday’s announcement, of the company’s coming-soon 22 nm process. That it was coming soon is no particular surprise; Intel showed off a SRAM-populated 22 nm test wafer two falls ago at the 2009 Intel Developer Conference, after all. And at last fall’s show, company officials briefly mentioned Ivy Bridge, the 22 nm-based ‘tick’ litho shrink of current-generation ‘tock‘ Sandy Bridge products, due to enter production by the end of this year.
That production schedule seems to still be solidly holding, according to company officials who participated in today’s briefing, and judging from the prototype server, desktop and mobile CPUs demonstrated running in systems. However, what was at least a little surprising are the transistor-level details of the 22 nm process. Below are two block diagrams of a conventional planar transistor, employed in prior lithography generations including the current 32 nm one:
And below is the tri-gate ‘3-D’ transistor that Intel will begin using at 22 nm, marking the company’s self-described most significant process breakthrough since 2007’s hafnium high-K dielectric:
Intel actually began publicly talking about its ‘3-D’ transistor work nearly a decade ago, done via test wafers (and circuits on them) using the then-leading-edge 65 nm process. In looking at the first two graphics above, you can see how as other transistor dimensions shrink, so too does the inversion layer between source and drain whose conductivity (or not) is modulated by the presence or absence of voltage on the gate. Smaller dimensions mean less current transferred during any particular period of time, thereby making it more difficult to distinguish an ‘on’ transistor from the background-noise leakage current of an ‘off’ transistor.
Therefore the fundamental motivation for Intel’s tri-gate transistor, so-named because it surrounds the ‘fin’ channel on three of four sides. For a given set of planar dimensions it provides a substantial increase in the surface area contact between the gate and substrate, much as a skyscraper holds a whole lot more ’stuff’ than does a single-story structure of the same foundation size. Intel’s spokespersons’ enthusiasm for the forecast results was palpable (even if they went out of their way, presumably for competitive isolation reasons, to avoid calling the transistor breakthrough a FinFET):
As you can see, both high-speed and low-power transistor variants will be possible, among other things differentiated by their operating voltages. It’s also possible to construct more complex multi-fin single-transistor structures in cases where even higher drive current, therefore performance, is necessary. One interpretation of the above data is that same-speed 22 nm transistors can run at lower voltages than their 32 nm precursors (0.8V versus 1V). And at the chip level, Intel believes that 22 nm tri-gate-based products such as Ivy Bridge will consume up to 50% lower active power than their 32 nm planar-based predecessors.
None of this comes for free, of course; Intel estimates that at least up front, a 22 nm wafer will cost 2-3% more than its 32 nm predecessor. Nonetheless, the company is determined to make tri-gate the process foundation for all upcoming 22 nm-based products, from high-end Xeon server CPUs to highly integrated Atom-based SoCs. Gordon Moore is apparently reassured that his Law will hold up for at least one more turn of the lithography screw; although he didn’t attend today’s event, here’s the quote he supplied:
For years we have seen limits to how small transistors can get. This change in the basic structure is a truly revolutionary approach, and one that should allow Moore’s Law, and the historic pace of innovation, to continue.
One final note, for any of you who might be confused; while tri-gate is strictly speaking a 3-D structure (i.e. note the silicon ‘fin’):
what we’re not talking about here is stacking multiple transistors (or more simplistically, die) on top of each other, as IBM and others are working on. Maybe we’ll need to wait for Intel’s next process to see this next-step breakthrough enter high volume production? And now, for your multimedia entertainment and education, here’s a link to the media kit containing background presentations and other documentation, along with a few Intel-supplied videos to wrap up: