Design Con 2015

Spare cell leakage minimization in physical design, part 2 of 2

-July 15, 2014

Continued from Part 1

Proposed flow for leakage power minimization

Spare cell insertion is a well known technique to reduce the cost of functional fixes, limiting the changes to a few metal masks. Common practice is to tie to ground the spare cells’ input pins, reconnecting them later in the flow, as required by any functional ECOs.

For illustration let’s take a NOR gate spare master which has 2 inputs A1 and A2. This gate will have 4 different states of A1 and A2 and hence four different state-dependent leakage power values. This gate would be summarized as shown in Table 1.

Table 1  State-dependent leakage power for 2-input NOR gate

Truth Table ( 2-input NOR gate)

Leakage Power (nW)

INPUT

OUTPUT

A1

A2

ZN

0

0

1

0.100143

0

1

0

0.019104

1

0

0

0.021549

1

1

0

0.012044

By referring to this table, the developed algorithm will find the minimum leakage value and associated input combination.

For a 2-input NOR gate, the minimum leakage value of 0.01204 nW is when both inputs are tied to ‘1’. In the same way, all spare logic can be connected to minimize leakage.

 

 

Figure 2: Spare cell leakage optimization Flow

 

Experimental results

The proposed flow was tested in 90nm technology using Synopsys’ IC Compiler for spare cell insertion in post-placed design, and PT-PX to report state-dependent leakage power of the spare cells. The results in Table 2 show the comparison between the leakage power consumption of the spare cells in the traditional flow in which all inputs of the spare cells are tied to ground, and the proposed flow in which the inputs of the spare cells are tied to the condition which gives minimum state dependent leakage. Also, overall combinational cells’ leakage power in a whole design is reduced as shown in Table 3.  The spare cells distribution of design “A” is shown in Figure 3.

Table 2: Spare cell leakage power reduction in design “A”

Design

90nm

Total Cell Count

112141

Spare Cell Count

9600 (8.56%)

Spare Cell Leakage (Traditional Flow)

534.656 nW

Spare Cell Leakage (Proposed Flow)

367.322 nW

% Reduction

31%

 

Table 3: Total combinational cell leakage power reduction in design “A”

Design

Total Combinational Leakage  Power

(Traditional Flow)

Total Combinational Leakage Power (Proposed Flow)

 Reduction (%)

90nm

2654 nW

2486 nW

167 nW (6.33 %)

 

 





Figure 3: Spare cells spread in design "A"

 

Figure 4: Spare cell (2-input mux) connections after routing


Benefits

  • This approach is safe, without any side effects, as it is only implemented on spare cells.
  • No runtime penalty
  • No complexity involved in implementation
  • The leakage value will change drastically if there are sequential spare cells in the design.
  • This approach can save more leakage power in lower nodes, where leakage is dominant in the overall power of the chip.


Drawback

Routing of spare cell pins will be different, as inputs connect to either power or ground, instead of only ground in the conventional approach.


Conclusion

In ASIC designs, there is a strong need to minimize static leakage power as much as possible through different techniques. The traditional way of connecting spare cell input pins to either power or ground rails does not assure minimum leakage, as it is state-dependent. In this article, we proposed a new method to minimize the leakage power of idle spare cells by connecting their inputs to a state which results in the minimum leakage power. This method was tested on post-placed layout, and the result shows a reduction of 31% spare-cell leakage power, and 6.33% overall combinational cell leakage power in the 90nm technology node. The future challenges include taking care of multi-voltage and multi-corner designs, and handling physical design challenges in the area of routing to ensure minimum changes to the mask.

 

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