Design Con 2015

MIPIs: They’re everywhere

-August 13, 2013

I see MIPIs: They’re everywhere. Every meeting I attend I see people wearing or using them. I have at least six, my wife has three, and each of my kids have one each.

In 2012 there were at least three billion of them floating around and by 2017 there’ll be 17 billion, according to the MIPI Alliance, which was formed to herd and train them how to behave and enable dependable and consistent communication between cameras, laptops, tablets, wireless, memory cards, and all sorts of mobile I/O devices.

I always knew MIPI (pronounced like “yippee,” but with “m” instead of “y”) ICs were “out there,” but I never really noticed how many or how challenging it was until I got talking with Shamree Howard, High-Speed Digital Program Manager at Agilent. She mentioned a webinar taking place today on demystifying MIPI M-PHY receiver physical-layer test challenges.

You’d think that with so many devices out there that MIPI implementation and test would be all figured out by now, but this is the constantly evolving world of mobile devices where the frontiers of performance, size, and power are constantly being pushed and optimized. According to Howard, as MIPI data rates surpass 5Gbits/s lane, on its way to 5.8Gbits/s and beyond, more and more engineers are having to focus on receiver testing.

“Many never had to work on receiver testing, but this is the trickier side of testing,” she said, especially as speeds increase with MIPI interfaces such as cameras, memory, and displays. Issues include interpreting the jitter requirements for each protocol, whether it be PCIe, DisplayPort, USB or UFS, as well as how to count errors.

According to Russ McHugh, applications engineer at Agilent, “The error counting is controlled by the protocol layer riding on top of M-PHY.  There are many different methods and which one is used depends on the protocol and designer’s choices.”

That variety of protocols and substandards makes testing the MIPI PHY really tricky. Howard herself took a stab at explaining the very confusing variety of protocols and how they relate to the PHY over on the DesignCon Community site in her piece, “MIPI D-PHY and M-PHY interfaces and alphabet soup.”

While that helps put things in perspective, it doesn’t really help the thousands of engineers who are heads down trying to figure out how to test at the higher-rate M-PHY layer. So Michael Fleischer-Reumann worked on a quick 1-hour course that’s going on live today at noon EDT/9 am Pacific that’ll help get you moving.

Entitled, "Demystify MIPI M-PHY receiver physical layer test challenges," the course explains the difference between D-PHY and M-PHY, its different revisions (up to 12 Gbits/s), and provide an understanding of how to overcome the physical-layer test challenges.

Enjoy and let me know what you think. By the way, is MIPI on your roadmap too?

Related topics:
Mobile interconnect standards on the move
PCIe takes on mobile, Thunderbolt, more...
M-PCIe: Utilizing low-power PCI Express in mobile designs



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