Profiles in Design: Thomas Pawlowski
J. Thomas Pawlowski is a fellow and chief technologist with Micron's Architecture Development Group. In this role, he evaluates new technologies and memory architectures. During his career, Pawlowski has helped develop numerous memory architectures and concepts, including synchronous pipelined SRAM, hierarchical cache systems, zero bus turnaround SRAM, the first double-data-rate memory (SRAM, and then DRAM and NAND), PSRAM, high-speed NAND, the first double-address-rate memory, the first quad-data-rate memory, the first multi-channel memory, memories on SERDES buses, and the first DRAM to exceed SRAM performance (RLDRAM).
Trained in electrical engineering at the University of Waterloo in Canada, Pawlowski holds approximately 150 U.S. and international patents and serves on several advisory boards. He will be a keynote speaker at the upcoming DesignCon in Santa Clara, CA, speaking on Thursday, January 30, 2014 from 12:00pm – 12:30pm PST in the Mission City Ballroom of the Santa Clara Convention Center. I thought it might be nice to get to know him a bit beforehand, and so I asked him to participate in our Profiles in Design series.
EDN: Why did you first get into this area/career?
TP: I chose moving into the area of memory technology and architecture way back in 1992 because it appeared to be the area that was in need of the most improvement.
EDN: What do you find fascinating about engineering?
TP: I love the combination of creativity and free thinking combined with the urgent problems that need solutions. What a privilege it is to do something so meaningful and be paid to have this much fun.
EDN: What has surprised you over the years in terms of technology?
TP: There are so many things that could be mentioned! One that stands out is the continuing cycle of thinking that the end of a technology is near and then finding ways of extending it.
EDN: What did you think we’d be able to do now that we still can’t?
TP: I’m surprised we are still in such a primitive state with computer interfaces.
EDN: What’s next for you/the industry?
TP: I wish I could say. The Micron Automata Processor, for example, had its architectural beginning in 2006 and only now can it be spoken of publicly. There are many things I have worked on between then and today. There will be a fantastic number of announcements coming in the years ahead, each of which will be unexpected, especially from a traditional memory company.
EDN: Any advice for new engineers?
TP: Think broad. You never know what will come next, so acquire the broadest skill-set you can handle. Too many people overly specialize. The most valuable people are the ones who can integrate the most different disciplines.
You can catch Thomas Pawlowski’s keynote on Thursday, January 30th at noon in the Mission City Ballroom at the Santa Clara Convention Center. His talk will cover revolutionary architectures, including the story of the Micron Automata processor and how to prepare for emerging memory technologies.
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