Deterministic Jitter for High Speed Serial Receiver Tolerance Testing

-March 08, 2012

The idea behind receiver tolerance testing is to submit the receiver to “the worst case but compliant” stress. If it can operate under those conditions, the thinking goes, then it can interoperate with any compliant transmitter + channel combination.

Standard applied stresses include some or all of these: a stress-inducing pattern, worst case rise/fall times, transmitter deemphasis, spread spectrum clocking, interference, random noise, interference or crosstalk emulation, random jitter (RJ), and some combination of deterministic jitter (DJ) or equivalently, bounded high probability jitter (BHPJ).
Most standards require a DJ in a combination of sinusoidal jitter and intersymbol interference.

Sinusoidal jitter (SJ) should be the easiest type of jitter to accurately apply. It is sinusoidal phase modulation. Many pattern generators incorporate the ability to apply SJ. If yours doesn’t, then you can use a simple arbitrary waveform generator and modulate the pattern generator’s reference clock.

SJ testing usually requires two steps. First, SJ at a frequency below the clock recovery bandwidth and with amplitude up to and sometimes exceeding a unit interval (UI). The second SJ test is at a frequency beyond the clock recovery bandwidth and at a substantially lower amplitude. The idea is to stress the clock recovery circuit in a way that assures that it can roll with the low-frequency punches as well as tolerate reasonable levels of higher frequency interference.
It’s also worthwhile to perform a few tests at frequencies that span the clock recovery roll off. The idea is to map the clock recovery frequency response. The specs don’t require this test, but it’s a good way to familiarize yourself with the part. While good old phase-locked loops (PLL) should respond predictably, some interpolating technologies can have weird resonant effects around the interpolating frequency boundaries near the roll off.

Intersymbol interference (ISI) is caused by the frequency and attenuation response of the channel. Since different sequences within a test pattern have different frequency content — for example, a long string of identical bits has more low frequency subharmonics while frequently alternating 1s and 0s just have the fundamental its harmonics — every logic transition within a test pattern can have a distinct trajectory. By trajectory, I mean the V(t) path the waveform follows in making a given logic transition. Since the specific ISI signature depends on the test pattern it’s called “correlated jitter” or “data dependent jitter.”

ISI is voltage noise, not phase noise, but since the different trajectories cross the voltage slice threshold at different times it causes jitter.

The specifications require prescribed levels of ISI in terms of a calibrated jitter backplane or an S-parameter template. Sometimes the specification is defined as an equivalent length of trace on standard fire-retardant type-4 (FR-4) media. Some spec’s (e.g., DisplayPort) simply require a minimum peak-to-peak ISI jitter level measured in unit intervals; in these cases, you might as well use a simple low pass filter to apply ISI. While circuits have arbitrarily complicated frequency response, their most obvious overall character is low pass.

The prescription of SJ and ISI imposes horizontal and vertical eye closure that tests several aspects of the receiver. The ability of the clock recovery circuit is tested at all relevant harmonic and subharmonic frequencies and its frequency response is checked with two SJ tests. the combination of vertical and horizontal eye closure confirms that the decision circuit, including any equalizer, is sufficiently sensitive for the system to perform at the maximum tolerable bit error ratio, usually 1E-12.

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