Test patterns are supposed to stress you out
Test patterns play critical roles in physical layer compliance testing by challenging different aspects of a system.
Receivers in HSS (high-speed serial) technology must be stable. When the average voltage of a signal varies, the receiver slice threshold shouldn’t wander. Most receivers are AC coupled, and the specs provide a time constant over which they should be robust to variations in short-term average signal voltages.
To stress baseline wander, the test pattern incorporates subpattern strings that vary the mark density (the ratio of the number of logic ones to the total number of bits) of the signal within the specified time constant. For example, a signal like 0100 repeated many times followed by 1011 repeated the same number of times provides back-to-back AC coupling stress while satisfying the overall mark density = 1/2 requirement. Lesser receivers will wander off under these temporary DC offsets and cause errors.
Embedded clocking is the breakthrough that gives HSS tech immunity to low-frequency jitter. By using a clock-recovery circuit to extract the system clock from data transitions, the time-delay of the sampler has the same jitter as the data it samples within the bandwidth of the clock recovery circuit. The result is that the sampler and the data it samples dance in harmony.
The more logic transitions in the signal, the easier it is for clock-recovery circuits to provide a clock that’s locked to the data. The specs require an average of one transition every two bits (a.k.a., a “transition density” of 1/2) and use data encoding to make sure the frequency of data transitions is sufficient to stay locked. For each data encoding scheme there is a maximum possible occurrence of CID (consecutive identical digit) bits.
Early generations of clock-recovery circuits used PLLs (phase-locked loops) and cheaper, digital variations on the concept called phase interpolators that had a rough time staying locked through a string of a dozen or so identical bits. The most common solution was to use 8B/10B encoding that guarantees at least one transition every 10 bits.
The introduction of DLLs (delay-locked loops) dramatically extended the ability to recover and lock to embedded clocks with CID runs of dozens of bits. Instead of 8B/10B encoding with its 25% overhead, newer standards use 64B/66B encoding that guarantees a transition just once every 66 bits, reducing the overhead to just over 3%. Scrambling is usually included, too, to reduce the probability of having long CID runs.
ISI (intersymbol interference) is the biggest predator in the HSS jungle and it presents a problem. The local frequency content of a signal varies over different segments of that signal. For example, a 00011100 sequence has more low-frequency content than a 10101010 sequence. The combination of the frequency content of the signal and the frequency response of the channel causes the waveform surrounding a specific bit to depend on the values of neighboring bits. In other words, symbols interfere with each other, hence ISI.
To provide sufficient stress for a compliance test, it’s important to include enough permutations in the test pattern. But if we’re not careful, as data rates increase, this requirement can make for ridiculously long test patterns. And ridiculously long patterns can stress test engineers more than the stress receivers, so I’ll return to this problem in detail next time.