The very short reach of 25 Gb/s
OIF-CEI has been working on a VSR (very short reach) IA (implementation agreement, which OIF-CEI’s version of a spec) to plug that hole. Remember, OIF-CEI doesn’t officially target a given technology the way that 802.3 targets Ethernet. The IA provides compliance agreements, like a standard, to assure interoperability. OIF-28G-VSR has not been published but it will be demonstrated at ECOC, here’s a summary:
• Unidirectional, differential lanes at 19.90 to 28.05 Gb/s
• 1 to N lanes on PCB
• 10 cm Serdes to connector + 5 cm connector to transceiver
Since OIF-CEI doesn’t explicitly target a given technology, the VSR IA also paves the way for 32GFC – the oddly named 28.05 Gb/s flavor of Fibre Channel.
The press release description says the demo “will feature host ASICs with VSR SERDES, host PCB traces, optical module connectors, module retimers, active copper cable assemblies, optical transceivers, host ASICs with LR SERDES, backplane PCBs and backplane connectors.” Including participation of seven companies: Applied Micro, Avago, Inphi, Luxtera, Molex, Semtech, and TE Connectivity.
The IA has separate requirements for the Serdes and transceivers. The idea is to go easy on the transceiver side to keep power reasonable, after all, they’re driving lasers.
Transmitters have eye height and eye width requirements rather than mask tests. Eye height and width are defined with respect to BER (bit error ratio), which is a nice way to remove ambiguity. Since most jitter analysis packages on oscilloscopes and BERTs (bit error ratio testers) provide BER contour diagrams, it’s an easy test in principle.
What makes it difficult/interesting is that all lanes have to be active and asynchronous to introduce crosstalk. To emulate the medium response, the tests require compliance boards between the transmitter and test equipment. With unit intervals of less than 40 ps, the signal is a mess after a few cm of PCB. The test equipment has to recover the clock and emulate a minimal equalization scheme, CTLE (continuous time linear equalization). CTLEs are filters that are peak 1-8 dB at the Nyquist rate. That peaking has the undesired effect of amplifying crosstalk.
Transmission channels have to meet a host of differential S-parameter and matching requirements that incorporate insertion and return loss.
Receiver testing is light on stress. The only defined stress is a sinusoidal jitter template to challenge the receiver’s clock recovery. The compliance test boards cause ISI (inter-symbol interference). Crosstalk isn’t specified other than that asynchronous signals are supposed to be active on other system lanes with different test patterns, but the levels of crosstalk are left to your imagination.
I asked why they didn’t include an interference tolerance test, like those required of the 10 Gb/s electrical channels in 100 GbE that balances insertion loss and integrated crosstalk noise. David Stauffer, OIF’s Physical and Link Layer Working Group Chair said, “It is not trivial to create a specification for crosstalk and interference that specifies the characteristics of the generated signal in sufficient detail to support a reproducible test. The SJ spec is a proven method in current and prior generations of CEI to generate jitter that cannot be equalized and thereby create margin for uncorrelated crosstalk and other effects.”
The proof is in the pudding, I mean, the demo, but crosstalk introduces high frequency amplitude noise and the SJ template requires the just 0.05 UI (about 2 ps) of timing noise above the clock recovery roll off. SJ doesn’t resemble crosstalk. So be careful out there!