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M-PCIe – Goin’ mobile!

-July 15, 2013

Like everything else in Silicon Valley, PCIe (peripheral component interconnect express) is goin’ mobile (cue up The Who). The big news at the June PCIe Special Interest Group Developers Conference was “mobile express,” M-PCIe.

The advantages of consolidating interconnect technology include the usual drivers—cheaper to develop, fast as you want, fewer specifications for developers to master, better power management—and you won’t need new drivers because every operating system already supports PCIe.

The essential ingredient to M-PCIe is incorporation of MIPI’s physical layer, M-PHY. It’s conceptually simple: replace the PCIe PHY layer with M-PHY and retain the rest of the PCIe protocol stack—data link layer, transaction layer, software layers and so forth.

Ramin Neshati, the PCI-SIG Marketing Workgroup Chair, said, “The scope of M-PCIe is limited to a small specification of about 60 pages.” Which is a tiny in comparison to the 860 page PCIe 3.0 specification.

M-PHY is a mobile-focused physical layer spec developed by MIPI, the mobile industry processor interface alliance, that is already prolific in mobile technology like tablets, smart phones, and thin laptops. The MIPI alliance welcomes the introduction of M-PCIe as a way to ease development and proliferate M-PHY.

Mahesh Wagh, an Intel PCI-SIG contributor, described M-PCIe as “an ECN [engineering change notice] that maps PCIe over M-PHY much the way that the USB-IF SSIC [Universal Serial Bus-implementer’s forum super-speed inter-chip] spec maps USB3 over M-PHY.”

M-PCIe does not cover form factor specifics and affects neither PCIe PHY nor M-PHY. M-PHY is designed for links up to about 10cm on standard FR-4 PCB.

Since the physical layer of the protocol stack specifies link training, M-PHY’s link training has been modified. This modification is essentially, the “M” in M-PCIe. Where PCIe has three generations, each specified by the rate of transfers per second--Gen 1.0 at 2.5 GT/s, Gen 2.0 at 5 GT/s, Gen 3.0 at 8GT/s, and Gen 4.0 (whose release is expected in the first half of 2014) at 16GT/s—M-PHY has three “gears”: gear 1 spans 1.25-1.45 Gb/s, gear 2: 2.5-2.9 Gb/s, and gear 3 (which has not yet been released): 5 Gb/s. M-PHY supports two independent reference clock rates, 19.2 or 26 MHz which is quite different from the traditional PCIe requirement of a 100 MHz distributed clock.

Further, M-PHY incorporates 8B/10B encoding at all rates/gears as does PCIe Gen 1.0 and 2.0. Since 8B/10B encoding incurs 20% overhead, it’s a shame that the overhead reduction achieved by PCIe 3.0 in going from 8B/10B to 128B/130B encoding couldn’t be preserved. Perhaps M-PHY gear 3 can take advantage.

All in all, the ability to leverage PCIe experience to mobile electronic design is a positive development. Of course, implementers of M-PCIe must be members of both the MIPI Alliance and the PCI-SIG.

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