PCIe Update: Power, IoT, storage, OCuLink, simulation, and equalization

-July 01, 2015

Low power, IoT, mobile apps, and anticipation of Gen 4 headlined the 2015 PCI-SIG Developer’s conference—though traditional PCIe applications on HPC (high performance computing) and PC (not as high performance computing) platforms remained the standard’s leading role. Looking a little closer at the tea leaves, I saw a lot of interest in simulation-measurement comparison and continued aggravation in trying to optimize clock recovery, equalization, and crosstalk.

First things first: PCIe stands for peripheral component interface express. It has been around for decades and shows every sign of fulfilling a prophecy made three years ago: “All future client-based storage attachments will use PCI-Express.”

When we say IoT (internet of things), what we really mean is low power and big data from billions of networked gadgets.

Ramin Neshati, Intel engineer and PCI-SIG’s Marketing Workgroup Chair, as well as the seer who made the above prophecy, emphasized that “The Low Power Initiative is not new!”  Half swing specifications that operate at 400 mW have been around since the 2.5 Gb/s first generation of PCIe. There will be a new 200 mW quarter swing state included in Gen 4. Their goal for standby L1 sub-states is to get down to microwatts.

PCIe has been going mobile for years with M-PCIe adapted to operate over MIPI’s low-power M-PHY.

PCIe’s prowess stands out in moving the massive amount of data created by IoT doodads. NEC had a handout with a graphic that I thought caught the situation: the physical world as a source of data from gadgets, monitors, surveillance, and all the things lurking around us whose data must find its way to servers and storage.

Figure 1: The graphic I cut from the NEC slide that was in the PCI-SIG press handout (hacked by Ransom, Copyright 2015 PCI-SIG).

Neshati’s prediction from 2012 about PCIe storage is embodied in NVMe (non-volatile memory express)—the spec for PCIe-SSD interconnects. The proliferation of SSD (solid state drive) storage renders several support features for spinning disks in SAS (serial attached SCSI; small computer system interface) and SATA (serial advanced technology attachment) nearly obsolete. Without that overhead, NVMe is a friendlier technology. Now add in SFF-8639 (small form factor) connectors that support everything, and PCIe makes an obvious hot-pluggable backbone for high-density SSD storage attachments.

Figure 2: Comparison of storage connectors (Source: Demartek.com)

The spec covering the best acronym in the business, OCuLink (optical/copper link) is out for final review. Neshati said that it’s “pretty much done.” Expect to see version 1.0 of the spec this autumn. OCuLink specifies wide bandwidth (up to 32 Gb/s in PCIe gen 3) cables that can be many meters long. It’s up to the manufacturer whether they use fibers or wires, as long as the cables comply with the signal integrity specifications.

I’m disappointed to report that I didn’t see any OCuLink cables at the exhibits. Samtec had several cables on display that use optical fibers for pristine data transfer across many meters with built in e-o and o-e convertors at the connectors but nothing labeled OCuLink.

You can tell what really concerns developers by how they spend their time—actions, after all, speak louder than press briefings. Since this is a quickly swallowable antipasto-like update, I’ll present the following two main-course topics in detail right here in my next two installments.

The first challenge, the primo, usually a pasta dish, isn’t new, but if the number of people working on it is any indication, no sure-fire solution has emerged. Every test and measurement company at the 2015 PCI-SIG dev conference featured tools for verifying system and circuit simulations.  

As simulation has become recognized as the better, cheaper, faster way to design circuits, their accuracy has become an ever more important question. The question is usually phrased: “How do I know if my simulation correlates to reality?” but it extends to analysis of real signals that are buried on chips, inaccessible to probing. We’ll cover this in detail next time.

The secondi, a nice New York bistecca, if you will, comes from the developers of PCIe gen 4, the 16 Gb/s version. Three separate presentations covered variations on the theme of how to optimize the combination of FFE (feed-forward equalization) at the transmitter—usually called de-emphasis—and clock recovery, CTLE (continuous time linear equalizer) gain, and number of DFE (decision feedback equalization) taps at the receiver. I’ll serve up some surprising results right here, with a side order of crosstalk. It should make a satisfying summer meal.

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