Your DesignCon 2016 dance card isn’t complete without…
If you don't attend these events…you'll never forgive yourself:
- Tuesday 19-Jan 4:45pm: The opening night Jitter Panel (a.k.a., Case of the Missing Eyes)!
Not just because it will be awesome, or because it's a great place to vent your frustrations on the test and measurement industry, or because all of your PAM4 fears/criticisms will be addressed, but because it’s Tradition!
- Complimentary Lunch!
To add the obvious cliché, tempted, I am.
- Eric Bogatin's boot camps, S-Parameters and/or High Speed Channel Design
If you hurry, you might get a seat and a free taste of what makes Eric a treasure for all of us. By the way, did you know his novel, The Shadow Engineer, has been revised and re-released, all new and improved?
- Wednesday 20-Jan, 9:20am: Channel operating margin for 56 Gb/s PAM4 chip-to-chip and backplane interfaces
COM (channel operating margin) is an important but complicated concept that isn’t going away. This looks like a great place to learn "fundamental principles of COM and its underlying link model" and see it in real applications.
- Wednesday 20-Jan and Thursday 21-Jan, 12:30-6pm: SWAG, free beer, Chiphead!
You can learn a lot talking to colleagues on the Expo floor, more importantly you can score some cool swag, drink some free suds, and hang with Chiphead.
Swag, free beer, and Chiphead: the real reasons you come to DesignCon (okay, maybe not Chiphead).
- 20-Jan and Thursday 21-Jan, 12:30-6pm: The Wild River Technologies booth where an amazing new training curriculum is being launched by a collaboration that includes a brilliant, amusing, and self-proclaimed signal-integrity sage, an astute Russian Genius, and a scary looking guy from Portland and his kind-hearted sidekick. (Okay, this is pure self-promotion. I can’t believe my EDN editor lets me get away with it.)
- Wednesday 20-Jan, 2:00pm: Jitter, Noise Analysis and BER synthesis on PAM4 signals on 400 GBPS communication Links
I've read this paper and, despite the really long title, it's awesome: a concise, complete, helpful description of the state of PAM4 signal integrity testing right now. Sure, during the transition from good old baseband NRZ/PAM2 to PAM4, testing will evolve and the equivalent paper in 2017 will look different, but this paper sets the stage.
- Wednesday 20-Jan, 2:00pm: PCB Probing for Signal-Integrity Measurements
Alternative title: "Is that a Probe in Your Pocket or are you just Happy to See me?" (Okay, I admit it, I don't know anything about this session, just couldn’t resist the bad joke).
- Wednesday 20-Jan, 2:50pm: Learn How to Turn Simulation into Reality for PAM4 Analysis
You kill two birds with one presentation here: upgrade your simulation skills and PAM4 understanding.
- Wednesday 20-Jan, 3:45pm: Optics vs Copper for in-chassis Connections @56-112 Gbps: is Copper Still a Viable Option?
Oooo, fiber optics at DesignCon! A panel with an all-star cast: Fields, McMorrow, Bogatin, Zivny, Verdiell, Goergen, and famous backup singers!
- Wednesday night in the Hyatt lobby/bar: toast to Steve Weir.
Steve was a truly unique individual. In some sense he exemplified the notion that engineering chooses people, people don’t choose engineering (except for sales and/or marketing engineers, of course). He was the sort of guy that needed to be a consultant because what corporate atmosphere could tolerate his intense focus on results with total disregard for process? Added benefit: discussing whether or not the stories Steve used to tell were true. You see, every year, he would corner a new suspect and begin a story: "If you tell anyone about this, I’ll deny it, but…"
- Thursday 21-Jan, 8:30am: Overcoming Power Integrity Challenges in Design, Characterization, and Debug of Digital Electronics
Awesome opportunity to learn about PI from someone with a deep understanding of everything. Heidi Barnes knows everything. Seriously, everything.
- Thursday 21-Jan, 10:15am: Signal Integrity Tips and Techniques Using TDR, VNA and Modeling
Bread and butter DesignCon, exactly why we come here and why we come back. Jeff Most has been doing this for a long time and always brings plenty of puns and bad jokes. Not to be missed.
- Thursday 21-Jan, 12:45pm:
If you're not on the SI-List e-mail list, just hit that link right now and everything will be okay. If you are, this is the chance to see the people who argue in your Inbox. Some of them owe you a drink for the time you spend reading their quibbles, but you also owe some of them a favor for the free consulting. Just go to Room M1
- Thursday 21-Jan, 1:00pm: PAM4: New Measurement Science for New Signal Technologies
If you leave early, you'll miss Teledyne-LeCroy’s mad scientist, Marty Miller, doling out a fresh perspective on signal integrity problems in PAM4 design and test. Marty has an amazing knack for providing new ways to think about old and new problems. On your way home, you will ponder this talk and say to yourself, "Why didn’t I think of that?"
- Thursday 21-Jan, 1:45pm: Meet up with authors Kenneth Wyatt, Steve Sandler, Eric Bogatin, and yours truly where we'll be selling and signing copies of our books.
- Thursday 21-Jan, 3:45pm: The Challenges of Measuring PAM4 Signals
Not only does a panel on PAM4 open DesignCon, a panel on PAM4 will also close DesignCon. My illustrious editor will moderate a panel where you'll learn from people who deal with simulation, measurement, and even production test of PAM4. You'll get a completely different perspective than you'll get from the Tuesday panel. You'll hear from the people who field PAM4 questions every day. Because one of the panelists works at an ATE company, you'll hear about how just getting PAM4 to work in the lab isn't enough. The best part is that this panel has a completely different set of panelists that the Jitter Panel. By this time this panel opens, you will have surely seen several presentations on PAM4 and will be ready to bombard the panelists with questions such as "are really you convinced that PAM4 will replace NRZ at 56 Gbits/s?"
Besides, can you really get enough PAM4?
Want to learn more? Attend DesignCon 2016, the premier conference for chip, board, and systems design engineers. Taking place January 19-21, 2016, at the Santa Clara Convention Center, DesignCon will feature technical paper sessions, tutorials, industry panels, product demos, and exhibits. Register here.
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