Into the OTN data stream at OFC/NFOEC
FPGAs have made their presence felt for years at the Optical Fibers in Communications/National Fiber Optics Engineers Conference (OFC/NFOEC), so it would be easy to breeze past the latest Xilinx preview of a demo at next week’s OFC as just so much puffery. But look again. As FPGAs move directly into multiplexer/transponder duties (what Xilinx calls a ‘muxponder’), the importance of reconfigurability for handling the bitstream becomes paramount.
If you’ve been paying attention to the 802.3ba high-speed group within IEEE, you know that Ethernet is following a two-way path to higher speeds, with OEMs developing 40-Gbit and 100-Gbit follow-ons to 10-Gbit/sec networks. But if you’ve watched the users of Sonet in the public network make similar plans, you know that many carriers want to retain the OTU2 signals (10G) from the current Optical Transport Network, and multiplex transport signals on top to achieve 40G and beyond. You might also be aware that storage area network specialists are looking for effective ways to multiplex Fibre Channel protocols into public metro networks. OTU2 is doubly problematic in this regard, as it does not have the overhead to carry 10G Ethernet or 10G Fibre Channel packets.
So the big play for FPGAs at OFC/NFOEC in previous years has been integrated logic and transceivers for MAC/PHY Ethernet devices at 10 Gbits/sec. Obviously, the mainstreaming of fast transceivers using 28-nm process technology allows FPGA vendors to integrate more ports into a single piece of silicon, but that’s not the key advantage to the Xilinx muxponder. Instead, the reconfigurability mentioned in the press release will help telecom equipment providers respond to a vast array of transceiver module alternatives (known as ‘MSA’s’, for multi-source agreement), which use a number of lane multiplexing techniques.
WAN equipment vendors must prepare for CXP, CFP, QSFP+, and a multitude of other interfaces for 40G and 100G networks. The most common lane multiplex alternatives likely will be x4 and x10, but other mux options cannot be ruled out. And a single device will be expected to handle multiple protocol types, from physical up to transport layer. This is where “partial reconfiguration” that does not interrupt the bitstream comes in. Xilinx will be showing an Avalon board, using dual Virtex-5 devices, that supports OTU-2, OC-192, and 10-Gbit Ethernet at the same time.
This is not a “Golly gee, look what my FPGA can do” demonstration. This is a preview of what all line cards in the 40G and 100G world will be expected to handle. Sure, we may see a few network-processor/ASSP combinations handle these functions. But it’s a realm where FPGAs are likely to shine.