NATURE abhors a nano-vacuum
Kudos to Princeton University EE Professor Niraj Jha for taking third place in the university’s Innovation Forum, recognizing research with commercialization potential. The award was described in an April 14 news release from Princeton. JJha was the developer of NATURE, a CMOS/nanotube architecture for FPGAs, which he first described in a 2006 paper for the Design Automation Conference.
Jha’s team recognizes the similarities between the FPGA architecture described in the NATURE paper, and the nonvolatile memory architectures designed by Nantero Inc. of Massachusetts, using ON Semiconductor as a development partner. To date, however, Princeton has not inked any deals with Nantero, nor with larger companies working with memories, FPGAs, or carbon nanotubes.
This brings up the point we’ve mentioned all too often in looking at FPGAs based on graphene memory, 3D interconnect, on-chip time-division multiplexing, etc. There are many ways to make FPGA programming blocks smaller, and make memory elements more power-efficient. Most of them require specialized manufacturing or CMOS process design techniques that are far from standard in the industry today.
Personally, I think that many carbon-based nanotechnology elements, including nanotubes and buckyballs, have unrealized potential compared to the breadth of uses to which they already are employed. But there are many practical hurdles standing in the way. Maybe the Princeton award and some online mentions will help Jha get the attention he deserves for the NATURE concept. But this is only the first step in a long path to practical implementations.