Teraflopping to the future
I’m excited about the future of computing with all the benefits that multicore promises. Before you start thinking I’m Pollyannaish, keep reading.
Yesterday at the In-Stat Microprocessor Forum, I sat through a number of presentations by Intel’s top technical folks, and what really caught my attention was Jim Held’s talk, “Beyond multicore: the dawning of the era of tera.”
Held is an Intel Fellow and director of the chip giant’s tera-scale computing research and he discussed in greater depth what I have written about in the past: the teraflops research processor.
The big picture is that this technology allows teraflops performance within a mainstream power envelope, Held explained, with a peak of 1.01 teraflops at 62-watts, and measured peak power efficiency of 19.4 gigaflops per watt.
Also the tile-based method allowed this processor to be designed with half the engineers in half the time.
I think the jaw-dropping aspect to the technology are the fine grain power management features that allow power to be scaled to match workload demands and features 21 sleep regions per tile.
Further, this power management pays off through hierarchical clock gating and sleep transistor techniques, up to 3x measured reduction in standby leakage power and scalable low-power mesochronous clocking, Held noted.
As great as tera-scale computing is, Intel’s next-gen Penryn technology is right around the corner – although I would like it for my laptop now!
Stephen Fischer, a senior principal engineer at Intel delved deep into the 45-nm Intel Core microarchitecture that promises enhancements for higher performance and improved energy efficiency along with new SSE4 instructions for improved video, imaging, and 3D content performance.
Fischer reminded that Penryn advantages include lower transistor switching power and leakage current for reduced idle power, longer battery life, and quieter systems. As well Penryn allows up to 2x improvement in transistor density for significant area scalability to support additional capabilities within the existing power and thermal envelope. And higher core and bus frequency allows for more performance in the same power and thermal envelope, Fischer said.
Users around the world (including me) are looking forward to reaping the benefits of Intel’s “Deep Power Down” technology and enhanced dynamic acceleration technology, which, in multi-core CPUs, uses the power headroom of idle core to boost performance of the non-idle cores.
Also make sure to check out EDN Contributing Editor Steve Leibson’s “Leibson’s Law” blog entries from the Forum as well.
-Ann Steffora Mutschler, Senior Editor
Currently no items