Live from ISQED: The Problems with SOC Design
Mentor’s Shankar Krishnamoorthy is a man who sees nothing but problems ahead for advanced SOC design. As Chief Scientist of Mentor’s Place and Route Division, Krishnamoorthy worries about the huge increase in design rules as design lithographies scale down. He presented his views in a keynote yesterday at ISQED (the International Symposium on Quality Electronic Design). Krishnamoorthy noted that as SOCs become more complex and as the number of tricks used to drive power consumption down (or at least hold it steady) increase, design tools need to deal with “multimode, multicorner” timing closure involving temperature, voltage scaling, interconnect performance, device performance, and operational modes—to list just a few of the variables. I might add on-chip variability to this list of bugaboos, because I think that’s a real headache in the making as well.
To reduce or at least control power consumption, said Krishnamoorthy, SOC designers are using clock gating, multi-Vt transistors, power gating, and DVFS (dynamic voltage and frequency scaling). At this point in SOC development, designers need to avail themselves of all of these design techniques and all of these techniques place additional stresses on the design tools.
Currently, said Krishnamoorthy, the clock tree provides the greatest opportunity for power reduction. Often, he said, the clock trees are overoptimized for speed, meaning they run faster than needed—the skews are smaller than the limits set by the designer. The cost of overly fast clock trees is excessive power consumption. Re-optimizing clock trees to bring the skews closer to the targeted limits reduces clock-tree power consumption and there are tools to re-optimize automatically.
Krishnamoorthy also discussed an interesting design philosophy question for SOC design: How large should a block be? Krishnamoorthy lobbied for larger blocks because larger blocks means fewer blocks, so there are fewer design decisions to make in the overall chip architecture. There might also be fewer designers needed with the use of larger blocks, as long as the design team can continue to support one designer per block. Without saying it, I took this statement to be in support of large commercial IP blocks for SOC design, in much the same way that board-level designers gravitated to LSI chips in the 1980s. To my way of thinking, that’s the fastest path to large team productivity gains.
Finally, Krishnamoorthy noted that the use of multicore processors in EDA servers promised significant performance improvements in SOC design team productivity. The effect isn’t linear because tool runs that can be performed overnight while designers sleep (they do sleep, occasionally) deliver significant productivity gains.
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