Xilinx Zynq EPPs: Leibson’s Law in action?
Steve Leibson - March 2, 2011
Back in 2001, Xilinx introduced the Virtex-II Pro FPGAs based on 130nm process technology. These FPGAs were the first from Xilinx to incorporate a hardened processor core. (Back then, it was a PowerPC core.) Fast forward 10 years. After telegraphing its punch at ESC last spring, Xilinx has just introduced the first four members of its EPP product line named Zynq. “What’s an EPP?” you might ask. It’s an “Extensible Processing Platform,” a new IC category Xilinx hopes to create. Think of an EPP as an embedded processor complex with an attached FPGA fabric. That’s a Xilinx Virtex-II Pro FPGA turned on its head so that the hardened processor complex is the focus of the device and the attached FPGA array is the accelerant. Oh yes, and the 300MHz PowerPC has been replaced with two ARM Cortex-A9 cores running at 800MHz each.
You can read about the Xilinx Zynq EPPs in more technical depth in Mike Demler’s article, but I want to address another aspect of the Xilinx Zynq EPP product line here.
Leibson’s Law says that it takes 10 years for any disruptive technology to be adopted by designers. That rule of thumb is based on decades of observation and includes the adoption of transistors, ICs, microprocessors, C for embedded design, etc.
It’s no secret that the hard-core processors embedded in FPGAs introduced 10 years ago have not been the smashing success one might have expected. Personally, I think there are some significant reasons for the lack of adoption including the wrong processor architecture, a poor bandwidth match between the processor core and the FPGA fabric, and tool-support/ecosystem issues.
Soft-core processors such as the Xilinx MicroBlaze and the Altera NIOS have fared far better. But in the end, it really doesn’t make much sense for a standardized processor core to be implemented as a soft core in an FPGA fabric. The processor ends up being too big by a factor of 20x (that’s the SoC-to-FPGA expansion factor you can pretty much always expect to see), the resulting processor is too slow by a factor of 10x considering the process technology used, and the operating power just isn’t right either. Hard cores are the way to go if you need a processor. I could list the reasons, but they’re both arcane and boring. They’re also irrelevant.
So did Xilinx get it right this time with the Zynq EPP family? I think so. First, the processor is not presented as an “FGPA helper” on the EPPs; it’s the main attraction. The FPGA fabric is billed as a “processor helper” because it permits you to build and attach high-performance peripherals to the on-chip processor complex. When the chip wakes up after reset, the hardened processor complex boots first and starts running code, then you get to configure the additional peripherals in the FPGA fabric. This model fits the one software developers are familiar with. It’s always a good idea to keep the software guys happy.
Second, the Xilinx Zynq EPPs feature dual ARM Cortex-A9 processor cores and ARM’s on a roll at the moment-just in case you hadn’t noticed. Xilinx picked a leading processor core with the leading ecosystem this time. STMicroelectronics is selling tiny microcontrollers based on ARM M0 cores in 2×2mm packages while TI, Broadcom, and others are trying to outdo each other by packing as many ARM cores on their chips as possible. The magic number seems to be four this year. Next year, expect that number to grow. In reality, ARM has made nearly an across-the-board conversion of microcontroller IDM’s from 8- and 16-bit architectures to 32-bit ARM architectures with the notable exceptions of Renesas and Microchip.
Third, although I haven’t tried the tools, Xilinx seems to have the tool story in order. There’s a $495 package for software developers plus the gargantuan ARM development ecosystem. There’s also a hardware design kit for hardware developers that should be familiar to anyone already developing with Xilinx FPGAs. The hardware development kit relies heavily on the ARM AMBA4 AXI4 interconnect scheme for bolting peripherals to the processor complex and it includes some standard IP blocks. That’s always a help.
For these reasons, I think we’re about to see Leibson’s Law in action here. After 10 years of gestation, Xilinx may have the recipe to mainstream the idea of a processor/FPGA mashup. Oh yeah, Altera announced last October that it had licensed ARM processor cores and that it plans to introduce FPGAs with embedded, hardened ARM Cortex-A9 processor cores. The company promised more details on the new ARM-based FPGAs in 2011 and published a white paper on the topic last month. This won’t be Altera’s first walk down the aisle with ARM: Coincidentally, Altera introduced the Excalibur series of FPGAs based on the ARM 922 processor core around 10 years ago.
There’s every indication that this product category is poised to succeed, according to Leibson’s Law.
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