Reconsider the electron: A new spin on memory

Original Equipment Manufacturers (OEM) have relied heavily on semiconductor memory for their leading-edge designs. Over many years, DRAM, SRAM and flash have become commodities and readily accepted to the point of design complacence. However, these days talk is centered on seeking out next-generation or “universal” memory technology. That diligent search is taking on greater urgency due to growing concerns conventional memory will no longer scale in the near future.

At the 90- and 65-nm technology nodes, DRAM remains relatively healthy, although its process is not compatible for embedded applications. At 45-nm, however, DRAM encounters some scaling problems.

At that feature size, the capacitor is not able to hold sufficient charge. Vendors are now trying to shore up that issue by applying three-dimensional charge elements and other techniques to create a larger capacitor. But even with those remedies, DRAM vendors are hedging their bets by creating alternative approaches to keep business as usual.

SRAM, like DRAM, is experiencing scalability issues at 45-nm, such as instability and increased leakage current.

Meanwhile, NOR and NAND flash used in growing numbers of consumer applications will incur endurance issues at the 32-nm node. That will happen in about three years, when semiconductor manufacturers will use this technology node to fabricate their chips. Endurance refers to the number of times a flash device can read and write. Currently, multiple-level cell (MLC) flash at 65-nm has endurance as high as 10,000 cycles. At 32-nm, however, a flash device’s floating-gate architecture cannot hold sufficient charge. Consequently, the device literally starts to lose its memory, and the number of read/writes is dramatically reduced.

As a result of these looming problems, memory chipmakers are taking newer non-volatile technology routes to achieve the “universal” memory goal. Phase-change or PRAM is most often mentioned as the top contender. However, its supporters are relying on exotic and production unproven Chalcogenide GST material for switching “1s” and “0s.”

Phase change, as the name implies, switches from an amorphous to crystalline state in 40 nanoseconds (ns), which is inordinately long to compete with SRAM. PRAM also experiences wear. The wear results from constant atomic movement in the material, leading to fatigue and subsequent limited endurance.

Magnetic RAM (MRAM) is another candidate. Most MRAM technology is based on first-generation magnetic field data writing, which supports fast operation speeds. The most pressing issue is in future ultra-fine processes; first-generation MRAM will demand very large write currents. To maintain its non-volatility, the MRAM’s switching field must be made larger as the bits shrink in size. That means larger currents are needed to produce those larger switching magnetic fields in order to effectively perform write operations.

With those issues aside, the sweet spot OEMs are targeting in the near term is 100 microamperes current per write. The non-volatile MRAM technology reaching this goal must also possess proven scalability and unlimited endurance, plus low power and high speed.

To achieve these objectives, the industry must get back to electronics basics, revisit the basic electron and recognize another useful quantum characteristic, the electron’s spin. It can be exploited just as the industry has used charge. While an electron’s charge determines how it behaves in an electric field, its spin determines how it behaves in a magnetic field. The charge of electrons historically has been used in electronics to store, manipulate and transmit data. But spin, the “spin-up and spin-down” states of the electron, have not been used widely until recently in hard disk drives.

A most promising technology, spin-transfer torque, uses the spin of the conduction electrons to manipulate tiny magnets inside a bit cell, which in turn, determines if the memory bit is a “1” or a “0.” Spin-transfer torque (STT) RAM is the newest technology based on this unheralded physics phenomenon. The basic difference between conventional MRAM and STT-RAM is MRAM uses increasing amounts of switching current as feature sizes scale down, while STT-RAM decreases the required current with scalability.

Simply by considering the basic electron and exploiting another quantum characteristic, the memory industry can expeditiously move forward without having to rely on capex to rework existing memory technologies, have doubts about newer and unproven materials, worry about single line suppliers, expend dollars unnecessarily for multiple royalty fees or how to continue lowering power consumption.

President and CEO of Grandis Inc., Farhad Tabrizi is a 23 year veteran in semiconductors and the memory business holding positions in senior management, design, marketing, supply chain management, business development, strategic alliances, and industry standard committee chairmanship.