Welcome - we have lift-off!

Welcome to Out-of-this-World Design, a new monthly blog discussing advances in Space Electronics and on-board signal processing techniques for telecommunication, navigation, Earth observation, broadcast and space-science payloads or platforms.

When I last attended NASA's MAPLD (Military Aerospace Programmable Logic Devices) conference in Washington DC, I had the privilege of meeting Eldon C. Hall, one of the creators of the Apollo Guidance Computer. This seminal spacecraft computer had an operating frequency of 2 MHz processing 16-bit data from 2k of RAM (magnetic core memory) and 36k of ROM (core rope memory). The entire CPU was realised using 2800 ICs, each containing two three-input NOR gates and implemented using resistor-transistor logic.

I thought I would start this blog by discussing digital processing: most mission types are now exploiting the benefits of on-board digital processing with telecommunication satellites baselining radiation-hardened, deep sub-micron, ASIC and FPGA technology offering aggregate throughputs of Tbits/s.

For many years, qualified, non-volatile, antifuse, FPGA technology has been in-orbit with the latest devices offering 500,000 ASIC gates, 20,000 registers and 40,000 combinatorial cells. Parts use SEU-hardened flip-flops realised using triple-modular redundancy.

Non-volatile, flash-based devices offer the advantages of re-programmability with acceptable radiation performance for many mission types. The ability to change the logic makes prototyping easier and allows the function to be altered in-orbit. The latest SRAM-based FPGA offers some impressive stats:

What are your views on space-grade SRAM-based FPGAs? Has anyone qualified the assembly of this 1752-pin device and what do you think of the ceramic, flip-chip, non-hermetic package? A new class Y is being considered! The absence of bond wires will reduce the parasitic inductance and capacitance of the connections to the die that have plagued some key, space-grade, analogue components. A suggestion for Hi-Rel semiconductor suppliers: please offer daisy-chain parts that are representative of the final package and thermal dissipation.

There's a V5QV FPGA currently bolted to the side of International Space Station assessing its radiation sensitivity as well as some others in-orbit.

The latest LEON CPU comprises a 7-stage pipeline, a two-level, Harvard, cache architecture capable of 1.7 DMIPS/MHz. The current LEON4 synthesizable core has come a long way from the initial design funded by ESA. A number of companies now offer floating-point DSP, LEON and PowerPC®-based sub-systems offering SpaceWire, Mil-Std-1553B, CAN, LVDS and serial interfaces for mission instruments.

Future blogs will discuss radiation effects and testing (why do QML parts not have to be SEE tested?), hardening-by-design, device qualification, standards, on-board signal processing techniques, signal and power integrity, circuit simulation for worst-case analyses, mixed-signal co-simulation, the RF processing chain, power distribution and new technologies that will advance spacecraft avionics, e.g., GaN FETs and bendy passives.