A comparison of space-grade FPGAs, Part 1

-June 09, 2014

Space-grade FPGAs are offered in three major process technologies: SRAM, flash and antifuse.

SRAM-based FPGAs are volatile and need to be re-programmed at each power-up. This eases prototyping and allows devices to be completely re-configured in-orbit. SRAM configuration memory can be sensitive to radiation effects which can potentially corrupt a design and alter the intended operation. Some space-grade devices use the standard, un-hardened, six-transistor, storage cell in the functional logic blocks, while more SEU-robust parts exploit the radiation tolerance advantages of a 12-transistor design at the expense of increased area and power consumption. Continued CMOS scaling has helped to alleviate these disadvantages somewhat.

Flash-based FPGAs are non-volatile, live at power-up, and can be re-programmed in-orbit. A floating-gate transistor is used within each cell which is immune to firm errors as exposure to radiation cannot generate sufficient charge to change its configuration state. Flash memory cells typically require two transistors resulting in increased logic density, shorter routing, smaller interconnect delays and lower power consumption compared to SRAM devices.

Antifuse-based FPGAs are non-volatile, live at power-up, but one-time programmable, which can present prototyping challenges. The antifuses which configure the interconnect are grown between the upper two layers of metal eliminating the routing channels and switching resources between logic modules. This results in increased logic density, shorter routing and smaller delays. Antifuse FPGAs also consume less static and dynamic power than equivalent SRAM devices.

Flash and antifuse FPGAs require additional processing steps compared to bulk CMOS, which has resulted in the specifications of these devices lagging SRAM-based parts by several generations. The increased capacity, the diversity of the resources, faster operation and lower dynamic power offered by deep-submicron, SRAM-based devices can offset the intrinsic energy consumption and logic density advantages of flash and antifuse parts.

Smaller geometries have resulted in less dynamic power consumption because of lower core voltages and smaller gate capacitances. However, ultra deep-submicron processes dissipate more static energy because of increased leakage and subthreshold currents.

CMOS scaling has improved the total-dose and latch-up sensitivity of space-grade microelectronics. Thinner gate oxides trap less positive charge while lower supply voltages and the reduced gain of the parasitic, bipolar, silicon-controlled rectifier bolster total-dose and latch-up immunity respectively. SEE mitigation has become more challenging as increased logic densities require less overall charge to disrupt sensitive locations.

Some space-grade FPGAs have been hardened-by-process, fabricated using a CMOS silicon-on-insulator process, or use an epitaxial layer to protect against radiation-induced latch-up.

Other space-grade FPGAs contain intrinsic architectural and circuit-level features to protect against upsets and transients. One supplier of SRAM-based devices has replaced the standard, six-transistor, functional element with a radiation-hardened, 12-transistor design shown below.


Figure 1: Standard and radiation-hardened SRAM storage cells.

In the conventional cell, a particle striking node Q may cause the latch to change state resulting in an SEE. In the hardened version, Q is represented at two different nodes and a strike at either cannot cause an upset. The number of transistors per latch has doubled, which can significantly reduce the available gate count in a given circuit area.

The flip-flops within antifuse FPGAs are typically triplicated and upsets due to single ion strikes are voted out by the unaffected latches.

Block RAM and configuration memory contain error detection and correction to protect against SEUs. To reduce the effects of multi-bit errors, some vendors have interleaved the layout of configuration memory such that physically adjacent errors are separated in the memory map. This makes errors appear as separate single-bit upsets enabling them to be repaired.

Not all configuration memory is critical to FPGA operation and one supplier allows users to define hierarchical regions in the design and partition this into essential and non-essential bits. Soft-error detection and correction focuses on those bits necessary for logic design and techniques such as scrubbing and partial configuration can be used to prevent the accumulation of configuration errors due to SEEs.

Some suppliers provide proprietary tools that automatically triplicate registers, combinational logic, voters, global buffers and I/O to protect against SEUs and SETs. State machines can be protected against SEEs by choosing fault-tolerant coding schemes and third-party EDA vendors also provide software which adds triple-mode redundancy to the HDL or during synthesis, e.g., Mentor Graphics' Precision.

It's important to note that FPGA SEE mitigation techniques do not prevent upsets nor transients, but allow designs to get through periods of error detection and correction without interruption, thereby reducing the effective FIT rate and increasing design availability.


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