A comparison of space-grade FPGAs, Part 2
Earlier this month some friends and I met to watch the opening match of the FIFA World Cup currently being held in Brazil. The host, a fellow electronics engineer, has a twenty-five-year-old Sony Trinitron CRT which still has superb picture quality – in fact, he owns almost two of these televisions, with a second in bits in his garage which he uses for spare parts. The same friend does not have a mobile phone, which I respect, however, this has proved to be very frustrating at times.
The match had just kicked-off, there was a lot of nice food and we were all having a great time when suddenly the screen went blank – 'blacker than black' in fact, if you recall the old Sony adverts!
There were lots of very unhappy people, swearing profusely, including four electronic engineers in a room full of nine, and it took three of us to lift the television onto the floor. Someone had the foresight to enable the 'live-pause' function on the digital box while we removed the back of the Sony Trinitron. My friend also happened to have a multimeter, an oscilloscope, and a soldering iron in his garage, and it took about forty-five minutes to understand the failure, locate a very dusty, char-grilled, power transistor and swap this with one from the spare chassis in the garage.
The television came back to life, we lugged it back to its original position and had a great time watching Brazil vs. Croatia (was that really a penalty?).
The 'SEFI' (single-event functional interrupt) that affected my friend's television got me thinking about the various SEE mitigation features used by space-grade FPGAs. Some mission types, e.g., telecommunication satellites, must provide continuous availability of service for the operator and its customers.
Older, space-grade FPGAs fabricated using larger geometries focused on SEU mitigation using a number of different hardening methods, e.g., triplication of registers, DICE memory cells etc. The softness of the combinatorial logic within these devices was generally ignored as the larger, parasitic, routing capacitances intrinsically filtered SETs. However, for the latest deep-submicron parts with increased logic densities and smaller interconnects, SETs can be the dominant SEE as the amount of charge required to affect sensitive nodes becomes less.
An SET is the voltage pulse resulting from the charge deposited by an ionizing particle (proton or heavy ion) passing through a sensitive area of a circuit. Each SET has a unique shape, polarity, amplitude and duration dependent on the location and energy of the impact, device biasing and output loading conditions. SETs can propagate in the asynchronous, combinatorial logic found within FPGAs and subsequently be clocked by a flip-flop becoming an SEU.
A number of factors determine whether an SET will propagate and result in an observable error:
Logical masking occurs when an SET generated by a particle is not propagated to an output due the logic value on the input of a gate, e.g., whenever an input of an AND gate is low, it will naturally reject a transient as shown below:
Logical masking of an SET
Electrical masking occurs when an SET is attenuated due to capacitive loading as it propagates along the signal path until it is no longer able to affect the output of a circuit as shown below:
Temporal masking occurs if an SET reaches a memory element at an instant other than the triggering window's setup and hold requirements. In the figure below, T1 is ignored but T2 is clocked to a flip-flop output.
Hardening-by-process, e.g., the use of silicon-on-insulator, triple wells, or buried layers, or hardening-by-layout, e.g., enclosed transistor structures or the use of guard rings, provide SET mitigation by limiting the amount of charge that can be collected at sensitive logic nodes preventing the formation of pulses.
Hardening-by-circuit design techniques use spatial or temporal methods to eliminate the effects of SETs. Hardware redundancy duplicates or triplicates combinational and/or sequential logic with the final output being a voted decision. SET mitigation is achieved at the expense of increased area and power consumption of the final circuit implementation. For the latest, deep-submicron FPGAs, although CMOS scaling has helped to overcome these disadvantages, increased logic density and lower operating voltages have reduced the critical charge necessary to generate an SET. This has increased the probability of charge sharing between devices and the potential of multiple soft errors resulting from a single particle strike.
Temporal techniques are being used by some space-grade FPGAs to prevent SET propagation, e.g., signals which are less than a given pulse width are assumed to be transients and such methods filter away any pulses in the data path that are less than a predefined width.
The use of guard-gate logic is a commonly used technique that combines spatial and temporal mitigation: an SET filter uses a chain of inverters to delay the signal along one path and a guard-gate to pass only those transients with widths exceeding the delay. The designer, therefore, has to balance electrical performance with radiation hardness: the wider the pulse, the lower the maximum frequency of operation.
The latest, space-grade, SRAM-based FPGAs use hardened registers to protect the functional logic and configuration memory cells against SETs. Control logic is triplicated and the flip-flop inputs within each programmable logic block can avail of an SET filter capable of suppressing pulses up to 800 ps wide.
For non-volatile, space-grade FPGAs, the latest flash devices place SET filters at register inputs to reject pulses. Antifuse-based parts triplicate flip-flops within a register cell with each sharing common data, clock and control inputs. Thus, the majority of SEEs in a hardened, antifuse FPGA originate as SETs in combinatorial logic, but become SEUs at higher frequencies as there is less time for transients to decay which subsequently get stored.
For all space-grade FPGAs, large global nets have optimised drive ratios and strengths making clocks and RESETs less susceptible to SETs.
Last month I compared the predicted power consumption of a twenty-stage LFSR implemented on various space-grade FPGAs. For a deep-submicron, SRAM-based device, the maximum speed of operation drops from 600 to 400 MHz when SET filters are used. For an equivalent, flash-based part, the highest frequency drops from 566 to 394 MHz.
I will discuss FPGA optimisation in future posts and how to improve the above performances, but I'm off to watch Uruguay vs. England at my friend's house who has promised to buy a new, OLED television and a smart phone if England reaches the final of the FIFA World Cup. There's absolutely no chance of this happening unless they get some Out-of-this-World help as shown in the following training video.
Until next month, stay SET free, enjoy the rest of the World Cup and hope to see you at NSREC!
Astronauts playing soccer on-board the International Space Station.