Die, component, package and PCB-level parasitics are adversely affecting the performance of spacecraft sub-systems. One notable example involved a mixed-signal device that generated an in-band spur at a fixed frequency due to internal crosstalk.
For the payload operator, this deterministic aggressor appeared within a communications channel directly impacting the revenue-generating ability of this area of the spectrum. In this specific case, the customer was able to conveniently allocate this bandwidth to a low-volume area over the Indian Ocean where the majority of traffic comprises blue whales feeding in these plankton-rich waters.
Space-grade semiconductors placed in hermetic, ceramic packages impact the performance of spacecraft sub-systems. Larger parasitics limit the usable bandwidth of devices and unwanted capacitances affect RF match, causing reflections which reduce the maximum-power and the level of in-band flatness that can be delivered to transponders.
The latest, space-grade FPGAs have stringent rise and fall-time requirements to support high-speed serial links. For the crystal oscillators which provide the timing reference, die and package-level parasitics must be managed to meet a mission's, overall BER and link-budget requirements.
As I explained in a previous post, the efficiency of switched-mode regulators is limited by component parasitics, e.g., ESR, ESL and FET on-resistance. Poor floor-planning, layout and/or a PCB stack that has not been designed-for-EMC, exacerbate the inefficiencies impacting overall, system-level operation, e.g., EMI, PSRR, loop stability, transient response, thermal management, clock jitter etc...
The above examples demonstrate the system-wide impact that die, component, package and PCB-level parasitics have on spacecraft operation and great care is required to deliver the performance that will enable the next generation of missions.
Not all parasitics are bad, however, and in some cases, prior knowledge of their existence can be used advantageously. In power-supply design, the ESR of the output capacitor is used to guarantee stability of a regulator and 'friendly' parasites can limit the overload current if the output from a DC/DC convertor was to become shorted for example.
In a switch-mode power supply, a parasitic inductance may be helpful when the FET is turned-on by limiting current spikes, but can be harmful due to the high-voltage pulse it creates across the switch at turn-off as it tries to release its stored, magnetic energy. An unwanted capacitance across the FET can be helpful at turn-off, but potentially harmful at turn-on, as it tries to dump its electrostatic energy inside the switch.
The switching noise produced by digital logic propagates through the substrate and power-distribution network to the sensitive, analog circuits degrading their performance. CMOS scaling has only made the problem worse because the larger number of transistors implement more digital functions, which in turn generate further noise into the bulk and power distribution.
Device scaling also increases the substrate-doping concentration to reduce transistor-threshold voltages. Consequently, the bulk conductivity increases providing a lower resistivity path for coupling. Furthermore, lower supply rails reduce the headroom and voltage swings in analog circuits making them more susceptible to noise.
When a die is placed in a package, its electrical performance is limited by the wire-bond self and mutual inductances. The former generates noise in the power distribution due to transient currents while the latter creates a path for signal coupling. Wire-to-wire capacitance also contributes to coupling.
Some of the latest, space microelectronic devices have been placed in flip-chip packages and a lot of good work by some vendors in collaboration with the Defense Logistics Agency (DLA) will see the creation of a new QMLY class for space applications. The electric path is much shorter in flip-chip packages and parasitic inductances and capacitances are smaller. Decoupling capacitors can be placed directly on the case as shown below, providing an a.c. shunting path to reduce the effective loop area (and inductance) of the power-distribution network.
Figure 1: Space-grade FPGA placed in a ceramic, flip-chip package.
The normal functionality of integrated circuits dynamically generates variations in the supply currents which flow through the finite impedance of the power-distribution network. These changes vary on-chip rails and the resulting power-supply noise affects the functionality and performance of neighbouring circuits on the same chip.
Noise generated by an aggressor circuit propagates to other circuits through the common substrate and through the power-distribution network. While these are the two dominant coupling mechanisms, parasitic inductances and capacitances generate crosstalk from one wire to another.
The bulk is shared by all logic and circuits fabricated on the chip and due to its semiconductor properties and finite resistivity, currents generate voltage drops across the volume of the substrate which then couple into other, nearby circuits. The effect of bulk noise on the functionality of victim circuits depends on the physical structure of devices and their topologies.
Adjacent circuits receive noise through the substrate and power distribution simultaneously and the following schematic shows a typical power-distribution network for a CMOS inverter in an integrated circuit:
The horizontally drawn R's and L's represent the parasitic resistances and inductances respectively of the chip, package and PCB interconnects, while the vertical RLC branches model decoupling capacitors.
Coupling can be reduced by limiting the amount of noise that is initially generated, preventing its propagation and de-sensitising the susceptibility of victim circuits. For example, lowering the parasitic inductance of the power-distribution network and the dI/dt of transient supply currents limits how much interference gets generated. The use of lightly-doped substrates which attenuate bulk noise faster, fabrication on silicon-on-insulator processes and hardening, guard-ring layouts, are techniques used to suppress the spread of substrate interference within space-grade microelectronics.
To enable the next generation of space microelectronics, a full appreciation of combined, system-level behaviours is essential to fulfil the aspirations of our customers and their stakeholders.
RLC parasitics, noise coupling and crosstalk issues at die, component, package and PCB level affect mission objectives that impact the bottom line of our commercial partners. To deliver the next generation of reliable spacecraft, future microelectronics and hardware designs must consider the overall, system-level impact of circuit topologies, technology selection, VLSI structures, floor-planning, pin assignment, analog-digital partitioning, place & route, power-distribution, the grounding strategy and the design of the package and PCB.
The above requirements must not be considered prior to tape-out or after fabrication when the cost of a re-spin will significantly affect cost and schedule. The impact of RLC parasitics, noise coupling and crosstalk must be considered during the initial architectural definition, together with the use of schematic-level simulation to provide an early prediction of any potential issues.
I'll be talking more about mixed-signal pre- and post-layout simulation to ensure designs are delivered right-first-time, to cost and schedule at Mentor Graphics' User2User Forum in Munich this November. If you need help managing your parasitics and understanding the sources of noise coupling, get in touch.
P.S. Thank you for all your emails on my previous articles on space-grade FPGAs and whether devices are being used on the Rosetta spacecraft currently orbiting Comet 67P/Churyumov-Gerasimenko. Actel (now Microsemi), antifuse A14100As are being used in the command unit and remote terminal. I'm really looking forward to seeing how this exciting mission develops and the exploits of the Philae lander!