Introducing the world’s first 28nm semiconductor for space, part 2
Following publication of the first article, many of you have discussed your on-board processing needs directly with Altera and asked them to offer a part with even more DSP resources. In response to your future mission requirements, I'm pleased to say that Altera has changed the part number to 5SGSMD5H3F35I4, a more DSP-centric FPGA, to support your projects.
The differences between the 5SGXMA7H2F35C2 and the 5SGSMD5H3F35I4 are summarised below with all other major logic resources, the package, and pin-out remaining the same:
It's refreshing to see a microelectronics' supplier engaging with the space-electronics community so proactively and listening to our needs. The specification of the 5SGSMD5H3F35I4, its range of logic resources and innovative fabric design, exceeds by several generations the speed, bandwidth, and power advantages of current space-grade ASIC technology. For the first time, space users will be able to avail of ultra-deep-submicron performance without having to pay large up-front NRE costs.
This month I will discuss Altera's, FPGA design software, known as Quartus 2, which allows you to input your design schematically, using VHDL or Verilog, or EDIF. The complete development flow from design entry, specifying constraints, synthesis, place & route, to programming a 'fitted' device can be controlled interactively using Quartus 2's GUI or script driven using TCL.
The Project Navigator window circled in green displays the project hierarchy, design files, the target device, and shortcut commands, while the Tasks window, highlighted in red, allows you to use the tools and features of the Quartus 2 software and monitor their progress using a flow-based layout. The Compilation Report window, circled in blue, summarises the status of the current project, while the Message window, highlighted in orange, displays information, warnings, and error messages.
Quartus 2 offers many tools to optimise a 'fitted' design and to help with hardware design, e.g. dynamic timing and power analysers, chip and pin planners, a logic analyser, JTAG debugging, transceiver and external memory toolkits, as well as access to Altera's IP catalog. A future article will discuss these features to assist with spacecraft sub-system development.
Altera offers a complete, interactive online tutorial to help you understand the Quartus 2 flow from creating your first project, design entry, specifying constraints, compiling your design, to programming your device. I encourage all readers who are considering the 5SGSMD5H3F35I4 for your next project to check out this valuable learning resource. The tutorial operates in three modes: Show Me, which teaches you, Guide Me, which requires input from you, and Test Me, which checks whether or not you paid attention to the guided instructions.
In addition to the online tutorial, an Introductory Guide to the Quartus 2 Software can be downloaded, which summarises the design flow, entry, synthesis, place & route, timing analysis and optimisation, programming and configuration, debugging, and EDA tool support. A comprehensive reference handbook is also available which describes in detail all the features offered by the Quartus 2 design software.
If you have any questions about using Quartus 2 or designing-in the 5SGSMD5H3F35I4 in your next space product, you can contact me via email or via my Linked-In group, Out-of-this-World FPGAs.
The next article in the series will demonstrate the SEE mitigation features available within the 5SGSMD5H3F35I4, including protection of the configuration and user memories, a syndrome register, which indicates the type and location of soft errors, SEU fault injection, and SEFI characterization.
Until next month, download Quartus 2 and start developing your next spacecraft sub-system!
- Introducing the world’s first 28nm semiconductor for space
- Introducing the world’s first 28nm semiconductor for space, part 3
- Are you bored with your board?
- A comparison of space-grade FPGAs - Part 1