SERDES testing for rocket scientists

-August 24, 2016

To support the development of high-throughput payloads, satellite manufacturers are exploiting the benefits of high-speed serial links to connect multiple FPGAs/ASICs on a single PCB and/or transfer data between modules. As bit rates increase, spacecraft OEMs are grappling with how to measure and characterise the performance and reliability of SERDES channels to ensure sub-systems are developed right-first time.

Previously we discussed the use of IBIS-AMI simulation to predict the performance and signal integrity of high-speed serial links before manufacturing your PCB. In this post, I want to share some experiences of using a bit-error rate tester (BERT) to measure and validate the hardware operation of SERDES links. You have spent many months designing your latest avionics, the PCB has been fabricated and assembled, the initial, power-up commissioning and basic functional tests have been successful, and you are now an eager beaver to measure the full performance and capability using the high-speed links.

For those of you not familiar with hardware testing of SERDES channels, a BERT sends a known data stream such as a PRBS down a link comparing the received waveform with the original. Any differences are noted and using this information, a bit error rate (BER) can be calculated for full, end-to-end performance, including the transmitter, the physical medium, and receiver.

As the space industry continues to exploit higher data rates, e.g. 5, 10 Gbps and above, the channel loss between the transmitter and the receiver, e.g. PCB traces, connectors, and cables, becomes more and more important because of high-frequency effects such as greater dielectric absorption, skin effect, and conductor losses. These result in intersymbol interference (ISI), i.e. distortion of the current bit due to the logic state of previous bits, increasing jitter, resulting in more data errors thus limiting the maximum data rate.

The latest BERTs enable accurate characterisation of multi-lane receivers and emulate channel loss by injecting various, controlled-jitter sources, common and differential-mode interference, transmitter pre/de-emphasis and receiver clock recovery/equalisation options. Sequences of data patterns such as PRBS, pulse, clock, static, and memory encoded using a variety of symbols, e.g. 8B/10B, 128B/130B, and 128B/132B, can be created to simulate the bit streams your avionics will receive during operation. In my case, I use Keysight's M8020A J-BERT to measure the performance of hardware SERDES links.


Here is the Keysight M8020A, 4-channel, 16 Gbps J-BERT.

As the space industry continues to exploit higher data rates, transmitters are using pre/de-emphasis to compensate for the electrical degradations and losses caused by PCBs and cables. It used to be, the faster the data rate, the shorter the distance, with speed inversely proportional to cable/trace length. Pre/de-emphasis is a signal improving technique that opens the eye at the receiver for point-to-point applications. It does not require any additional time, maintaining the efficiency of the link for data transfer, but boosts output current during transitions to speed up edges (pre-emphasis), or decreases the low-frequency components of a signal (de-emphasis). Consequently, the received waveform exhibits less ISI after its high-frequency content has been attenuated by the channel. The M8020A offers up to eight taps of pre-emphasis to provide eye-opening enhancements to overcome link losses and/or extend the reach of interconnect as shown below.


Transmitter pre-emphasis function overcomes channel losses.

All high-speed digital receivers are specified to tolerate a certain amount of ISI and the M8020A provides integrated and adjustable ISI to emulate loss on all channels during receiver characterisation as shown below.


You can preset adjustable ISI frequency and loss points.

For connectors other than SMA, test adaptors can be purchased to convert between the former and your preferred connector type. To provide you with further information, a Getting Started Guide can be downloaded as well as a User Guide for the instrument and system software. There is also a very helpful, short video which shows the generation, analysis, and GUI capabilities for the M8020A, and demonstrates live how the quality of the eye at the receiver can be improved using de-emphasis or degraded by adding controlled-jitter sources.
   
BERTs are win-win for the test and space industries: module-to-module SERDES characterisation has become quick, repeatable, highly controllable, mission independent, and can be performed early in the product development cycle to de-risk PCB layout, hardware connectors, and cables. Measurements can be controlled using scripts to automate production testing and BERTs allow you to sign-off the development of your satellite sub-systems with confidence and deliver your avionics right-first-time, to cost, and schedule. Here is a photograph of my bench:


An M8020A J-BERT connected to a DSAV334A Digital Signal Analyser.

It's time to get back to my BERT - speak to our colleagues at Keysight if you wish to evaluate their M8020A. I'd love to hear about your SERDES physical-layer measurement experiences and until next month, may your eyes always remain open!

P.S. The first person to tell me how a Bathtub Curve relates to an Eye Diagram will get a free Courses for Rocket Scientists pen. Congratulations to Lothar from Germany, the first to answer the riddle from my previous post.

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