Circuit dynamics puzzles
Dennis Feucht - December 15, 2012
Most of the time it is necessary to simulate circuits on computers to predict with sufficient accuracy what their behavior will be when implemented. However, a good circuit designer wants to have some theoretical insight into circuit behavior so that design decisions (including what to simulate) are rationally guided by some understanding of circuit dynamics.
In this article, a couple of possibly troubling circuit dynamics obstacles are posed as they might be encountered by an engineer designing BJT amplifier circuits. They are presented to prepare you for a series of articles on circuit dynamics, beginning next year. An answer to the first puzzle will emerge from the series.First Puzzle
For the first design puzzle, consider the following single-supply amplifier with bipolar voltage range at its input.
It has an inverting feedback loop followed by some additional gain. The loop itself is analyzed by first choosing the error and feedback quantities. The feedback quantity is easy to choose as vf = ve2. This is the voltage fed back and is the loop output quantity.
In the classic inverting op-amp, the feedback divider, Rf, Ri forms a means for combining vi and vf, and the same equation applies for a discrete-BJT amplifier. The error voltage, vE, which is the input of the forward path of gain G is the divider output, unloaded by the Q1 base:
Ti is the attenuation of the divider at the input, and it is outside of the feedback loop. The input voltage to the loop is Ti·vi. The reverse attenuation of the divider, H, is the gain of the feedback path, from loop output, vf, to the G input.
The error summing block of the classic feedback block diagram is implemented at the circuit level by the divider loop around which both input and fed-back quantities sum by superposition. (Often they sum in a loop by KVL for voltages or at a node by KCL for currents.)
When the quasistatic gain derivations are completed, the gains of the forward-path (G) and feedback-path (H) can be found. Quasistatic partitioning of circuits into blocks of the feedback diagram is sometimes challenging for circuits with spaghetti-like interconnections. It can be even more difficult to separate dynamic effects into the right blocks.
The open-circuit time constants (OCTCs) of G include τe1, τc1, and τe2. A general, single-stage BJT amplifier without additional reactances for frequency compensation has two BJT capacitances; Cc (or Cμ) is base to collector and Ce (or Cπ) is base to emitter, as shown below.
OCTCs of the output block following the loop, To(s), include τL2 and τe3. What of τc2? Is it in G or To? It will only be in one or the other because it is only one time constant. Cc2 causes Q2 base capacitance that forms a time constant with RC1.
It also involves RC2. If it is within the loop, loop gain will cause it to migrate. If in To, it is open-loop and appears in the amplifier transfer function as its given (open-loop), fixed value. In which block should it appear, and why?Second Puzzle
A second possible conundrum encountered in circuit dynamics involves root-locus diagrams for determining where the poles of feedback circuits migrate. One of the root-locus rules is that as quasistatic loop gain increases, poles migrate toward and terminate on zeros. If a circuit has a right half-plane (RHP) zero and a LHP pole, with increasing gain can the pole cross into the RHP as it migrates toward the zero? If so, the circuit becomes unstable.
I’ll spare you the wait on the answer in the hope that it will increase your interest in the coming series. Migrating real poles never cross from the LHP to the RHP. The closed-loop gain cannot have a pole at the origin.
For G → ∞, A →1/H, which is a finite and non-zero closed-loop gain. For the uninteresting case of G = 0, then A = 0, and there is a zero at the origin. For there to be a pole at the origin with a finite H, G would have to change signs. That is a quasistatic change, not a dynamic one. A remaining question is how RHP zeros affect the stability of a closed-loop feedback circuit. Hint: they are definitely not favorable.