The InterModule Bus
Microcontroller-based systems with analog I/O can be simplified by modularizing them as stackable boards interconnected by a minimalist bus. The InterModule Bus (IMB) is a master-slave bus controlled by the μC module. It provides a common channel for information exchange between μC and modules. This article defines the bus. It is being used in a new product to be announced with a MC56F8036 μC, and also with a Mitsubishi M3850 (6502 core) μC. It is a bus designed to minimize interface logic (one or two ICs) and connections (20-pin IDC).
Bus Connector and Pin Assignments
The bus connector is a 20-pin IDC connector with the following pin assignments:
The bus connector symbol is shown below, corresponding to pin locations on the physical connector.
Pin 1 is the leftmost, outer pin when viewing the connector from the edge of the board. Pin 2 is the leftmost inner pin, farthest from the edge of the board.
An input to the μC is an output to a module. To avoid confusion, all inputs and outputs are as viewed from the μC. For instance, SOUT is the serial output of the μC and SINP is the μC serial input.
A module is a set of functions. Modules are implemented on one or more circuit-boards. The bus can support up to 4 modules connected to the μC.
Each module is selected by module addressing. The module address lines, MA2-3, select one of 4 modules. Within each module, an optional register decoder can select up to 4 registers per module. Device or register selection is addressed through the MA0-1 lines. Together, MA0-3 select both module and register. Unless stated otherwise, MA0-3, taken together, will be called the module address because it selects both inter- and intra-module registers. When the μC has set valid addresses on these lines, the address select line, /SEL, is asserted low, causing the address decoder of the selected module to assert and enable its device decoder. /SEL asserts low and then unasserts high while MA0-3 are valid. Thus, either edge of the /SEL line can be used for clocking bus-related devices.
The preferred device for decoding module and register addresses is the 74HC139 dual 2-to-4 decoder. The first decoder decodes the module address; the second decodes the register address. The preferred implementation is shown below for module 0. U4A decodes MA2-3, the module address. One of four decoded outputs is asserted low. The one corresponding to the module number (0 through 3) is connected to the enable input of the second decoder, U4B. (For configuring module assignments, these decoded outputs can be jumpered.) Then when the module is selected, Y0 goes low, driving the /EN input of the second decoder (at pin 15) low, enabling its outputs. Register address MA0-1 is then decoded. One of four decoded register outputs is selected. Here, register 2 (Y2) is shown in use. It might connect to the clock input of a quad flop or (low-asserted) latch input of a latch, or to the output enable input of a quad buffer.
When module addressing is unasserted, all module output devices (which provide μC inputs) driving the bus lines should unassert and present a high impedance (hi-Z) state to the bus lines.
This simple module addressing scheme requires only one IC to implement, leaving more board area for module implementations.
The parallel bus (PB) can transfer four bits (or a nibble, half a byte) in parallel on lines PB0-3. Numerous MSI logic parts, such as those of the 74HC, 74HCT, or 4000 series are nibble-wide parts. Bus addressing is used to select the register of the transfer. Before the addressing cycle is executed, for an output transfer, the PB0-3 lines are written to by the μC. For inputs, the μC reads the PB0-3 lines some time after /SEL asserts low and before it unasserts high.
The preferred device on modules for nibble output is the 74HC175 quad D flop. It has a reset input and both true and complement bit outputs for each nibble bit in. The complemented outputs can reduce external logic. To input a nibble from a module on the PB, the preferred module output part is the 74HC125 nibble-wide buffer with three-state outputs, or 74HC244 or 74HC467 dual nibble-wide buffers. The clock line can be driven directly by the decoded register output of the 74HC139 decoder.
The PB data transfers have no handshaking protocol whereby either μC or module would signal the other when data is valid or when it is ready for data. This must be accomplished by timing. Because /SEL is driven by software, the bus is relatively slow and there is plenty of set-up time for typical devices accessing the bus. μC PB output nibbles are timed by /SEL. It is only μC inputs that are unsynchronized and occur when /SEL occurs. For synchronization with module events, inputs can first be latched into a buffer register on and by the module, then transferred to the PB when the register outputs are enabled onto it. The preferred device that includes in one package both register and tri-state output buffer is the 74HC873 latch or 74HC874 D-flop. These are dual-nibble parts.
Microcomputer I/O often includes counter-timers and PWMs. To accommodate these on the IMB for additional versatility, the parallel bus has a dual function. One IMB pin (2) is dedicated as counter I/O, CNTR0. PB3 is optionally CNTR1 I/O and PB0-2 are PWM0-2 outputs. Alternative use requires that dedicated inputs from modules be able to be gated off the bus with a tri-state buffer or else, for a given system, the pin is dedicated to a CNTR or PWM function. Some μCs have more dedicated function lines than the IMB can support and must be interconnected through an additional dedicated intermodule connector.
The serial bus (SB) transfers data one bit at a time using shift registers. IMB pins 3 through 5 constitute the serial bus. /SEL remains asserted and MA0-3 remain valid during serial transfer so that the serial device on the module is addressed. Three transfer lines are used by the SB: one for data output from the μC and input to a module (SOUT), one for output from a module and input by the μC (SINP) and a clock line to shift the data bits (SCLK). Using the SPI interface, MOSI is SOUT, MISO is SINP, and SCL is SCLK. Multiple bytes can be transferred between a selected module and μC. The word length is not limited.
SCLK shifts bits on the falling edge of the SCLK line. Consequently, output bits are stable on the rising edge of SCLK. Module input bits are clocked on the rising edge of SCLK. The μC inputs bits on the rising edge of SCLK from modules driving the SINP line on the bus and outputs bits on the falling edge of SCLK
The typical μC has several ADC inputs. These can be connected to the bus as four single-ended “analog pipes” AN0-3, used with the analog ground return, AGND. The ADC external voltage reference input, VREF, is also on the bus. It is essentially the full-scale voltage of the ADC inputs, and 0 V (analog ground) is the zero-scale end of the ADC input-voltage range. These pipes can be used as programmable analog interconnections among modules and μC. Their use is not limited to μC ADC inputs but can also be used for automated interconnection of modules.
In their default use, the pipes are bus-multiplexed μC ADC inputs. Multiple modules can have access to up to 4 ADC inputs when selected to input to them. Only one bus module should output onto these pipes at a time to prevent conflict between sources on the bus. Additional μC ADC inputs are interconnected through a separate dedicated connector or else analog-multiplexed on one or more modules.
The module bus is versatile in allowing one or more modules to be added to the bus. For the μC to configure for the modules on the bus, it must be able to poll the module address space and read back what kinds of modules are resident at the given addresses. Consequently, register 0 (REG0) is dedicated to module identification on the parallel bus. Modules output a four-bit code that identifies the module type. Up to 16 distinct kinds of module types can be placed on the bus, with further expansion made possible by allowing type 15 (all ones - no bus connection) be a default to the serial bus REG0 shift-register chain for μC input of an undetermined number of serial ID bits. Connection of the SB to a EEPROM selected by REG0 can provide additional module data. It is necessary for the μC to be able to handle all types of modules according to their ID numbers. Nonvolatile ROM (NVROM) such as EEPROM can provide uploadable module driver software to the μC.
Accompanying the InterModule Bus is a four-pin power bus connector, also daisy-chained along with the IMB but as a physically separate connector. This separation increases functional versatility for those occasions when power must be applied to a module without the IMB connected or without IMB use at all.
The power bus is a 4-pin SIP header with pin numbers following the ascending voltages. Pin one is on the left when viewing the connector from the edge of the board that it is closest to and parallel with. From pin 1 to pin 4, the pins are in ascending order of voltage: −12V, GND, +5V, +12V