Hot Chips panel looks for inflection point in silicon scaling
The traditional evening panel discussion at the Hot Chips Conference this evening took on one of the perennial bogymen of the semiconductor industry: Are we at an inflection point in IC scaling, and if so what should we do about it? The panel took up the first question primarily.
Of the panelists, Xilinx’s Michael Hart was perhaps the most sanguine about an inflection point. Hart acknowledged that processes were getting more expensive, and that as a consequence the foundry industry was consolidating, and he recognized that technology problems were getting harder to solve. But he maintained that scaling was still healthy, and would remain so for another five to ten years.
In contrast, IBM fellow Brad McCredie suggested that we had been seeing inflection points for some time. "In about 1990 we stopped scaling oxide thickness and voltage," McCredie said. "Now, moving forward takes a lot of money and a lot of hard work." But he suggested the next inflection point might be that in the near future the technology playing field will level out, with not that much different between the features of different processes. "At that point, it’s the guy with the bright idea that matters, not the bucks to buy the hottest process," he conjectured.
Tacitly acknowledging that the performance gains on individual transistors were leveling off, Texas Instruments OMAP guru David Wit contrasted the position of a handset designer to that of a CPU designer. The latter, he suggested, must figure out how to somehow use all the free transistors he gets with each new process node to get more general-purpose performance. But the handset designer, looking at a laundry list of new functions and enhancements to basic functions, both of which cry out for more transistors, has no such trouble. "When I look forward, I see nothing preventing our move to greater parallelism as more transistors are available," Wit said. "We can add real 3D graphics interfaces, and 3D audio. We can exploit air interfaces like LTE to move gigabits through the air. All this is possible, but it will require an almost crazy amount of software development and system design to do it. The expense will be great, and maybe only a couple of companies can stay on the treadmill."
Lode Lauwers of IMEC took a quite different tack, reviewing the growing menu of technology options that IMEC and its partners are researching. "The number of new technologies and new materials we work on is going up with each new generation," Lauwers said. He illustrated with just the short list of new materials, ranging from germanium implants to III-V materials to graphene, under consideration for sub-15nm transistors. Similarly, he gave a laundry list of new materials and structures for RAM cells, and pointed out that IMEC was investigating two approaches to advanced lithography, although he was quick to emphasize that the organization still has the most faith in the eventual triumph of EUV. Finally, he emphasized the growing importance of not just scaling, but adding new kinds of devices, from sensors and actuators to optical interconnect, on top of a conventional IC, and of developing true 3D IC technology. Lauwers concluded that there was no inflection point coming, just an increasing diversity of technology opportunities.
But Stanford professor Mark Horowitz gave the dissenting view. "We are at an inflection point now, but we are in denial about it," he proclaimed. He then listed two functions he sees inflecting. "First, technology is continuing to scale, but performance and energy consumption are not," Horowitz said. He argued that clever tricks, rather than scaling, had produced the modest performance and energy gains in recent nodes. "Second, the cost of design is increasing too rapidly. There are no ASICs today; every design has to be a standard-product so you can recover the cost of the design. I think in reality this is the most important problem, and we have to face it soon."
In a secondary discussion, panelists disagreed about the evolution of the industry. Lauwers suggested that given the sheer number of alternative technologies that are under investigation for 15nm and below, it was likely that we would see significant divergence in process roadmaps among the remaining process developers. Hart disagreed, pointing out that CMOS processes have all become pretty similar, and that the limited number of both companies capable of funding a new process development and equipment suppliers to work with them would necessarily push the industry toward a single roadmap.
Taken together, the comments seemed to suggest confidence in our ability to solve the scaling problems going forward, but declining confidence in the rewards we would receive from that progress. And there was universal concern that the escalating costs, both of process development and of design, would fundamentally rewire the industry.