Cadence launches another initiative: this time the subject is mixed-signal design
Ron Wilson - April 17, 2009
About three years ago, anticipating the changes that low-power design would impose on the digital CMOS design flow, Cadence helped bring together the Power Forward Initiative. The idea was to pull all the major stake-holders in low-power design flows together into a group that could talk about problems, alternative solutions, and common formats. While the initiative hasn’t turned out to be exactly a rallying point for competing EDA vendors—my quick count shows only three other EDA members in the group—it has attracted major SoC, IP, library, and foundry players. And arguably, the initiative has made significant progress in defining the problems in low-power design and forging a flow to deal with them.
Now–according to Cadence group senior vice president Chi_ping Hsu, who has been responsible for the care and feeding of the initiative within Cadence—that effort is reaching maturity. Hsu says that about the only major topic the group still has to address is the really thorny one of dealing with design hierarchy in a power-management flow. So it’s time for the energetic Hsu to start looking for another initiative to champion.
And he has settled on one: the Digital Mixed-Signal Initiative. The idea both leverages a market strength of Cadence’s and addresses a very real need in the market. Hsu says, and installed-base figures certainly back him up, that Cadence has a strong position in mixed-signal design with its Virtuoso platform. But he laments that the industry has never found a straight-line implementation flow that can produce a chip with both digital and analog blocks. Today all the solutions require two different branches, one for analog and one for digital, with very different flows. New-product announcements over the last few months have focused on stitching the two flows together without gaping discontinuities, rather than on unifying them.
Hsu envisions the Digital Mixed-Signal Initiative as, like its predecessor, a multi-year, multi-party program with an ambitious aim. But in this case, he says, the program will take more time. "Unlike Power Forward, this will be a five to eight year program," Hsu said. The aim is to produce a single design flow, without isolated branches or major redundancies, that can produce a chip with tightly-coupled analog and digital circuitry.
It’s none to soon to be starting, as design trends may be forcing the EDA industry’s hand. Designers point to the need for increasing integration at the system level as forcing more precision-analog and RF circuitry onto one die. But they also cite two other trends. First, as designers take on precision-analog design at finer and finer geometries, it’s taking more and more transistors to do what a handful of big, higher-voltage parts could do a few years ago. It’s not uncommon today for a single analog functional block to have thousands or tens of thousands of transistors, a startling number of them actually in the signal path. Second, because those fine-geometry transistors are, in many ways, really poor transistors and subject to relatively huge variations, digital calibration, digital compensation, and even digital signal feedback have become vital tools of the analog designer. Such architectures are a nightmare if you are facing them through a pair of disjoint design chains.
It might be ideal to start over from a clean sheet of paper and create a really mixed-signal environment, all the way from behavior-capture through physical verification. But Hsu thinks that is not the way the initiative will evolve. "I think the tools will evolve based on what customers tell us they need," he said. And that will likely be incremental changes rather than a sweeping reform of the flow.
As an example, Hsu cites Cadence’s recent change to it logic simulation engine: the simple-sounding modification to let the engine support real numbers in addition to a small number of logic states. This has the potential to merge some representation of continuous-time signals into a logic simulation, as well as to provide some analog-like treatment of such logic-signal issues as voltage sag and switching transients. A next step might be equally incremental, Hsu suggested. It would be nice if the analysis tools in the back-end flow could handle multiple technologies in a single pass, rather than having a separate suite of physical analysis tools for each type of circuit in the design.
Such ideas will probably be the bread and butter of the Digital Mixed-Signal Initiative. "The underlying problem is design complexity, and the need for increased automation in the flow," Hsu observed. "And the difficult part of that often is that there are big differences in the abstractions used by analog and by digital designers." Don’t look for revolution, but do look for a gradual polymerizing of disparate tools into a single– maybe too twisted, but single—chain leading from functional intent to analog/digital implementation.