Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform
Ron Wilson - May 1, 2008
Despite years of effort and millions of dollars in venture capital, analog design below about 180 nm remains more art than craft in most areas. At this point most efforts at analog synthesis have been abandoned, the closest remaining practice being rapid parameterization of some specific designs templates. And the problems are just getting worse as geometries shrink: transistor models are more complex—and early in a new process’s existence, less accurate—while parasitic impedances continue to grow relative to explicit impedances, and process variations increase. None of this makes traditional analog flows incorrect, but each of these elements increases the scale of the computing challenge.
Cadence, whose Virtuoso Platform has all but defined custom analog design for many teams, is dealing with the growing complexity not through revolution, but through evolutionary adjustment to its existing flow. The most recent step in this program, announced yesterday, comprises a set of changes, some of them previously announced.
The first of the changes is to the ADE environment: a method of attaching constraints to the design files early in the flow to later guide place and route tools in dealing with parasitics. The idea is that the designer will use his or her experience with a particular circuit topology to estimate where parasitic capacitances and resistances are likely to be a problem, and then will perform what-if analyses—generally based on PVT corners—to estimate the sensitivity of the circuit to these parasitics. The designer would then annotate the design files with constraints specifying the maximum parasitic R and C that a particular node can tolerate. This information goes to the downstream tools that actually do the placement and routing, where accurate extraction and editing are possible.
The second change bundled into this announcement is a mostly-previously-announced set of accelerations to the Spectre simulator. These include Turbo, which uses a combination of new time-stepping techniques, a multi-threaded model evaluation module, and, on the GXL version, intelligent pruning of RC parasitic paths from nets, all to increase simulation speed and accuracy. This speed increase is helpful in any case, but is absolutely essential for Monte Carlo analysis of full circuit models.
Third, Cadence has integrated its—again, previously-announced—space-based routing program with Layout Suite GXL, and developed a faster-executing P-cell tool called Express PCells. Both improve throughput in exploring implementation alternatives.
The theme here is not to find a silver bullet to doing analog design in the presence of increased parasitics and variations, but rather to make an iteration through the tools fast enough that designers can do meaningful exploration—both for an initial design and for the design-centering task that has become more and more complex with the multiplicity of process corners, growth of models and proliferation of parasitic paths. It’s pragmatic rather than inspired, but I suspect that’s what most analog designers would say they need right now.