SPIE and the IC design world: a wall starts coming down
Ron Wilson - February 11, 2008
If you want a graphic indication of how much the wall between SoC design and chip manufacturing has come down, take a look at SPIE. This conference, more formally SPIE Advanced Lithography 2008, has for years been the premier place where lithography specialists talk to each other about how to make patterns on wafers. It has been all but unapproachable for chip designers or EDA engineers unless they happened to have a background in physical optics.
But increasingly, and this year may be the inflection point, SPIE has been concerned as well about the impact that lithography is having on the IC design process. For the second time this year, there will be a track on design for manufacturing, with papers specifically addressing how the design process must deal with the new world presented to us by the realities of lithography. As an indication of how deeply design concerns have penetrated into this formerly specialized conference, Michael Rieger of Synopsys is the track co-chair, and at least seven of the papers will have EDA-industry authors.
All of this suggests it’s time to take a look at just how far the wall has come down. We are now well past the point where process-integration engineers could tell physical designers all they needed to know by giving them design rules decks. And we are arguably past the point where it was sufficient for physical designers to simply scan the design with some sort of tool, identify so-called hot spots, and fiddle with them until the tool said they were OK. We are now in a world where the back-end design tools must have internal, calibrated models of the lithography and CMP processes so that they can predict the features that will actually appear on the wafer, extract electrical properties from those features, and change the mask patterns as necessary to get within electrical requirements.
That has required that the process engineers’ Process Compact Models (PCMs) be condensed into more specialized, and must faster-executing, design models. The tools must use these models in place of rules to estimate whether the patterns will produce acceptable features on the wafer. To a large extent, this is because pattern-dependency has increased beyond the ken of simple rules. “If you take two 45 nm designs, both DRC-clear, you can get very different yields,” warns Cadence senior director of marketing Nitin Deo. “The errors in features on the die are pattern-dependent.”
This has led, Deo says, to a three-stage attack on lithography and CMP issues. First, their is an avoidance phase, in which the design tools attempt to get everything correct by construction, using DfM-optimized cells and DfM-aware layout and inter-cell routing. This phase is necessary just to ensure that there will be a manageable number of issues. Second, after model-based tools identify DfM issues, the designers will attempt repairs within the grid framework, probably decreasing the grid pitch. Finally, problem areas that have resisted fix within the grid framework will be attacked with gridless tools, making only incremental changes to keep the design database from exploding.
These measures can produce designs that are likely to be robust with respect to variations in lithography and CMP. But there are new challenges on the horizon. One of these is that etch variations are also becoming important. They can, however, probably be accommodated into the litho models, according to Cadence director of product marketing Bob Naber.
Another source of trouble will be pattern dependencies in the stress engineering that determines the carrier mobility—and hence the performance—of the transistors. Since the stress is created by external structures above, below, and around the transistor, it is pattern-dependent. As geometries have contracted, these dependencies have reached beyond the individual transistor, and by 32 nm will reach beyond the boundaries of a single cell. At this point cell designers will be unable to ensure that their cells will exhibit sufficiently low variations independent of placement. Back-end design tools will have to deal with them explicitly. “Today, the only way to model stress accurately is the TCAD tools used by the process engineers,” Deo says. “We will have to get this information into more compact models.”
Another serious issue will be double-patterning. As Naber explains it, in order to achieve higher feature densities on the wafer, lithographers are moving to using at least two separate masks to print a single layer. But how to decompose the patterns coming out of the end of the design flow into two or more separate masks per layer is another non-trivial problem, and it’s a place where there has to be a two-way flow of information between IC team and process team. On one hand, the process team has to understand the decomposition process well enough to create patterns friendly to it. On the other, decomposition has to take into account the fact that separating the data into two masks will create overlay variations, and those variations must occur only in areas where they can be tolerated. So mask-makers may have to understand the function of the geometry they are splitting up into a pair of geometries. They must not, for instance, split up two lines that define a critical dimension that cannot stand the addition of overlay error into its variation budget.
The growing need to move information in both directions across the old wall is changing this world. Increasingly, EDA vendors are in the business of extracting small executable approximations from TCAD models or PCMs, calibrating them against silicon, and embedding them into DfM tools. Increasingly, mask makers, lithography, and CMP engineers are having to understand the electrical function of the features their tools are creating. Deo sees the EDA vendors as the resource in the middle, attempting to translate for and minimize the impact on both parties.