Nanometer CMOS process variations: are they inevitable, or a symptom or immaturity?
For some time now it has been assumed by a lot of people that the growing process variations at advanced CMOS nodes were an inevitable result of physics, and therefore, like death, taxes and presidential election campaigns, inescapable. That is probably true in some cases. But old hands at process development are beginning to cautiously speak up to say that many of the variations designers face today can in fact be dealt with by improved process controls. They add that the adaptive controls needed for this effort will go beyond current practice.
ST Microelectronics Crolles2 Alliance director Joel Hartmann illustrated both cases—the probably inevitable and the not-so-much-so, in his plenary talk at ISSCC this morning. His points form a decent rule of thumb for separating out the inevitable from the unenviable. (For another comment on Hartmann’s talk, see here, and for a broader discussion of process variations at ISSCC, take a look at this entry from Brian's Brain.)
Hartmann’s illustrations of the probably inevitable involved, significantly, atomic-scale structures. “In a 16 nm MOSFET, there are 53 silicon atoms and 3.5 Boron ions in the channel of the transistor,” he stated. At this level, purely random variations in the number of atoms in the area—more or less independent of the accuracy of the lithography and etch processes—would result in variations in saturation drain current. No known process, short of atom-by-atom construction of the channel with an atomic-force probe, could prevent variations at this level. Similar arguments could be made for the tiny number of atoms in the gate dielectric layer, or for that matter on the bottom surface of the gate.
However some variations are not foreordained by such factors. Hartmann pointed to one increasingly difficult problem involving the height of the fill put into shallow-trench-isolation trenches. Measurements have shown that minor variations in the step height between this filler and surrounding topography can cause significant variation in electrical parameters in the neighboring transistors. But these variations in step height are a known problem from chemical-mechanical polishing (CMP,) and are dependent on position on the wafer.
Hartmann showed data demonstrating a significant reduction in this variation by measuring the step height after CMP and adjusting the duration of the following etch step to keep the steps of similar height. One process control link, and a significant source of electrical parameter variation goes away. Similarly, Hartmann showed that significant variations in interconnect metal thickness across a wafer could be traced to differences in pad velocity during CMP, and could be sharply reduced by actively varying pad pressure during the CMP process.
Can in-line metrology and feeding forward of data on variations eliminate all variations? Of course not. When the mechanism causing the variation moves from nanoscale to atomic scale, perhaps nothing can be done. But stronger, adaptive process controls may make the problem of designing with a few remaining variations much more manageable than what today threatens to confront chip designers, perhaps even bring variations back within a range that could be effectively controlled by design rules. That would be a welcome piece of news.