3D and power is all wet

-July 19, 2012

There has been a lot of talk recently about 3D ICs and the challenges associated with them. One area that contains some of the biggest challenges is related to power – how do you get power in and how do you get the heat generated back out again. To understand this a little more, I talked to Madhavan Swaminathan who is the Joseph M. Pettit Professor in Electronics at the School of Electrical and Computer Engineering and Director of the Interconnect and Packaging Center (IPC), an SRC Center of Excellence, at Georgia Tech, Atlanta. He is also the Founder and CTO of E-System Design.

I featured the introductory chapter of his book “Power Integrity Modeling and Design for Semiconductors and Systems” during my EDA Designline series about power in April. This book chapter provides a good background into the power delivery network and its analysis.

What follows is part of the interview.

Bailey: Please tell me what you are working on these days.

Madhavan: I focus primarily on the packaging side. With 3D ICs, one of the major issues is how do you design the interposer that acts as the interface between your 3D IC stack and let’s say the back of the printed circuit board. I have also been looking at the stacking of the ICs themselves, trying to get the power in and get the heat out.

Bailey: Xilinx has been telling us that the heat problem may not be as bad as first thought because the Through Silicon Vias (TSVs) are acting as pretty good heat channels.

Madhavan: That is true. If you look at the approach that Xilinx is taking, that’s the 2 1/2D approach. What they do is to take their FPGA chip, partition it into smaller chips, and then they interconnect them together using the silicon interposer. When you do that, the backside of the chip is still available for you to remove the heat. And as you rightly pointed out, silicon, especially the silicon interposer, is a good conductor of heat. Also the TSVs have copper in them and that is also a very good conductor of heat. In the case of Xilinx, they have access to the backside of the chip to get the heat out. Now as you start stacking chips on top of each other, the true 3D integration, then it becomes very, very challenging because now the heat gets trapped, and it is not able to escape from one IC to the other.

Bailey: Do you see any solution on the horizon to deal with this?

Madhavan: It depends on the application. If you look at the mobile space, the amount of power that is being dissipated by these ICs is fairly small, and therefore, the heat flux is small. An example is the Wide I/O Memory kind of an architecture, where you have a memory chip stacked on a logic chip, and you can use standard thermal management solutions to get the heat out. But as you get into high performance, where you want to stack a logic chip on top of another logic chip, and each one of these logic chips, is let’s say, an FPGA or a microprocessor, then the heat gets trapped. To the best of my knowledge, today, the only known solution that we have is a water cooled solution. And obviously, that’s not going to fly. Because imagine trying to build these laptop computers with 3D ICs with a water pump in it. But today, that seems to be the only rival solution because of the high heat flux involved, and that’s why I keep saying trying to get the heat out is a major issue that needs to be tackled, as we get into the stacking of higher powered chips.

Bailey: So you are saying water cooling is the only solution but at the same time it is not viable.

Madhavan: Exactly. At this point in time, people have demonstrated, including Georgia Tech, that you can cool the chips by creating micro-channels, creating hollow TSVs that serve as a pipe to pump water from the printed circuit board into these micro channels, and you get that heat out and you basically build up a closed loop system. And using that, you can bring the temperature of the ICs down, but obviously from a system standpoint, this may not be a cost effective solution, and people are looking at other ways to solve the problem, and to this day, I haven’t seen a rival solution yet.

Bailey: So are 3D ICs sunk (pun intended)?

Madhavan: Absolutely not. If you look at the semiconductor industry, you’ve been able to scale no matter what, and every time we hit a road block, we were be able to find solutions to it. A classic example is the power leakage problem in the mid 2000s where we were able to solve it by moving to multicore processors. I believe the same thing will happen over here where the power management solution and the thermal management solution would have some innovations in them that would allow us to stack these chips on top of each other and have them done at speed. But clearly, innovations are required both from a technology standpoint as well as from an architectural standpoint to get these to work. And I don’t believe we are there yet.

I will be publishing other parts of this interview in the future.

Brian Bailey – keeping you covered

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