3D NAND flash is coming

-November 15, 2012

Flash memory has very quickly risen from being an obscure memory type to perhaps becoming the dominant memory type for many devices, including music players, cell phones, tablets and now increasingly servers and mainstream PCs. But flash memory does not scale quite as well as the more traditional DRAM that it is replacing. It is thought that DRAM can scale down to 1nm whereas we are already hitting some problems with the scaling of the floating gate in NAND flash. It is not thought that planar NAND can go below 10nm which is only a couple of processes steps away from where we are today.

There are several other types of memory being developed, including spin-torque MRAM and Resistive RAM (ReRAM) that may replace both RAM and flash in the future. Another exciting direction is 3D NAND structures. In some respects this is similar to FinFET development for traditional transistors that are finding their way into 20nm and 14nm processes.

Toshiba is one company pushing 3D NAND processes with its p-BiCS (pipe-shaped Bit Cost Scalable) technology. The thought is that rather than lay the cells flat on the surface, higher densities can be achieved by stacking them on top of each other. This is shown diagrammatically in the figure below. As you can see this is not the same as 3D ICs where multiple substrates are layered on top of each other and connected using through silicon vias (TSV), this is building cells on top of each other to create U shaped bit lines. They currently have 16 layers devices where the hole size is 50nm and Toshiba says that the process becomes cheaper than the traditional NAND processes when more than 15 layers are created. Samples are expected next year and volume shipments by 2015.

Applied Materials has been working on etching systems that will make this kind of vertical stacking possible – driven by the demand for 3D NAND. According to Applied Materials, building 3D NAND structures in like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata. They say that today’s etch systems are just not able to rise to the challenge. Avatar, the new system, can achieve smooth vertical sidewalls without bending or warping and can transition smoothly between alternate stack layers. Another challenge is stopping at the right point when etching contacts on the NAND “staircase.”

Macronix is another company working on 3D NAND and they will be talking about the first working 3D NAND flash memory at sub-40nm in the upcoming IEEE International Electron Devices Meeting (IEDM) taking place December 10-12 in San Francisco.

They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a “staircase” bitline contact formation method. The result is an eight-layer device with a wordline feature size of 37.5 nm, bitline feature size of 75 nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20-nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25-nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

Brian Bailey – keeping you covered

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