A sneak peek into DesignCon
Brian Bailey - January 2, 2013
On Wednesday Jan 30th at 8:30 we have a paper titled Power/Ground Bump Optimization Technique on Early Design Stage, written by Youngsoo Lee and Dongyoun Yi from Samsung.
This paper described Samsung’s on-chip power/ground bump optimization technique that they use in the early stages of chip design stage using IR/DvD effect. It includes power map creation and optimization techniques that enable their designers to predict power noise as well as determining an optimal power and ground bump topology. This paper described the procedure, provides results comparison and shows how the proposed optimization method is validated from silicon to system level and the comparison results on co-analysis covering a chip, package and board.
Following this at 9:20 is a paper titled 3D Si Interposer Design and Electrical Performance Study written by a host of folks from Rambus and Industrial Technology Research Institute Taiwan (ITRI). They describe a silicon interposer that has two active dies on top and one active die on the bottom. The double-sided RDL layers and TSVs on this Si interposer provide die to die signal connections and vertical/lateral power delivery. They provide studies showing electrical performance and design strategies suitable for this configuration. Different types of transmission lines (stripline, microstrip line, and CPW line) are studied based on measured results and they provide correlation with modeling results from a 3D field solver. This study provides design guidelines for signal routing and signal integrity up to 20GHz.
At 10:15 there is a change of pace from looking at the very low-level aspects of chip design to verification at the very high level in a paper titled Cracking the Challenge of SoC Low-Power Verification written by Thomas Anderson of Breker Verification Systems. This paper looks at several techniques that are used for power reduction including the establishment of power domains that can be independently controlled. Power shutoff is used for domains not currently needed for the applications being run. Although simple in concept, the verification of SoCs using power shutoff is a significant challenge. This paper looks at a technique that generates self-verifying C test cases that run on the embedded processors in simulation and exercise a wide range of functionality while turning the power domains off and on.
To round out your morning at 11:05 is a paper titled Multi-Level Hierarchical Flow for Giga-Scale ASIC Designs written by Shashank Prasad and Kamal Preet Singh from Cadence. I didn’t get to see a preview of this paper, but I have seen similar papers from them in the past and I am sure it will be very interesting.
After some lunch you get to enjoy High-Frequency TSV Failure Detection Method with Z parameter at 2:00, written by Joohee Kim, Daniel Jung and Joungho Kim from Korea Advanced Institute of Science and Technology (KAIST).
This paper introduces a TSV failure analysis and detection method using a high-frequency measurement of the Z parameter. This paper proposes an electrical test method to improve fabrication yield of a 3D IC looking at TSV failures such as connection failure, insulator failure and conductor failure. From the failure modeling and analysis, the failure masks can differentiate between the failure types and the sensitivity of the proposed failure masks are demonstrated by considering fabrication process variations.
And finally at 2:50 you can enjoy How to Improve Power Integrity on Analog-to-Digital Converter (ADC) with Chip-PCB Hierarchical Structure written by several authors from KAIST. Analog devices are sensitive to noise and devices such as digital devices, power circuits, and antennas are noise sources. Analog and digital have to be integrated in the latest SoCs. Because of noise it can be hard to achieve high performance in these mixed-signal systems. This paper models and analyzes power integrity on mixed-signal systems. They use a 4-bit flash-type analog-to-digital converter as the system application. To validate the model and analysis, the design was fabricated in a 0.13 μm CMOS process and interconnected to the designed PCB.Oh, and did I forget to mention, you don’t have to move to enjoy all of these papers, They are all in Ballroom B, so just sit back, relax and be prepared to learn a great deal of highly valuable information.
Brian Bailey – keeping you covered
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