Fab lite, Design lite

-July 23, 2013

It must have been twenty years ago when Cypress Semiconductor came up with a revolutionary business model. Before then every semiconductor company had a design team and a fab. They were totally integrated in a vertical sense. Many of them developed their own EDA tools, but that was already on the way out. It was a lot more economical to have an EDA company amortize the cost of tool development over several design houses and to allow that form of specialization. It was a difficult transition for some because standards did not exist at that time and so required the adoption of new methodologies, languages and tools. Then Cypress asked the question – why do I need a fab. They are expensive to build and maintain and require a lot of expertise that would be better handled by someone else. At the time most people thought they were crazy. The companies with the fabs would surely cut them off as soon as they had a capacity squeeze. Of course, the rest is history. Very few design houses have their own fabs these days and even Intel is basically renting out space in their fabs. This was a significant change in business model and made companies much more capital lite.

The next change was brought about by the introduction of Intellectual Property. This started with processors and a few commodity blocks. The processors took specific expertise and the commodity blocks added no value to the final product. Bringing those components in as fully designed and verified blocks saved time and money and allowed the companies to specialize even more. The lack of standards slowed the rate of adoption, and we are still working on getting all of those in place today. Over the next ten years, the number and size of the IP blocks grew and today may fill 80% or more of the chip surface area and be made up of a hundred or more instances. This again made the design houses leaner and requires less capital.

Today we are seeing many design companies struggling with the back-end of the design process. The number of EDA tools they require goes up with each new node, the time they spend doing physical design increases and the nodes are coming at a faster rate, meaning they have less chips that are on any one node before they have to move to a new one. This means it is becoming difficult for many of the smaller companies to get the knowledge and experience necessary to optimize their designs and so I believe we have another transformation at the early stages of happening. The notion of RTL hand-off from a design house to someone who has the experience to perform the physical design is going to become a necessary business model change over the next ten years.

So, a design house will still have to come up with the idea, make the architectural choices, verify the design at the system level, produce an implementation at the RT level, or some pieces of it may have been synthesized from a behavioral description. They will then work with an implementation company to turn that into reality. That implementation company will be able to amortize the cost of EDA tools over a greater number of designs, have experts who oversee a greater number of designs and so build up more experience with the tools and the requirements of the fabs. Will this have an impact on the EDA companies? Possibly, but making deign cheaper will mean that more companies will be able to make them so they could be selling more tools at the end of the day.

What do you think? Is this a good or bad step for the industry?

Brian Bailey – keeping you covered

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