Design Con 2015

You can’t fix what you can’t see

-August 20, 2013

Nobody can deny the insatiable demand for smart phones and increasing functionality is going into every new generation of them. In order to bring those devices to you, smaller form factors are necessary and lower power consumption is demanded. This is in turn driving the fabless semiconductor ecosystem into ever faster migration to the newer technologies and adoption of smaller nodes that can help the semiconductor companies meet the consumer demands. But this is putting a strain on the system. Perhaps you can remember, not so long ago, the rumors, news reports and dire predictions that 28nm would never be able to yield sufficiently. Those stories have since been put to bed and 28nm is now yielding quite nicely, at about the same rate as other technologies. While yields are design dependent, most high volume components are yielding in the 80%+ range. Yield figures for memories are likely to be higher, but other types of design may continue to yield at lower levels. The same stories will raise their heads again when 20nm, 16nm, 14nm and 10nm first start coming in quantity.

In order to get to the necessary yield levels, the fabs have to understand what is going on in the fabrication process and the things that are causing yields to fall, and of course you can’t fix what you can’t find, and can’t control what you can’t measure. This is where companies such as KLA-Tencor come in with their process control and yield management tools. These tools play an increasingly important role in characterizing the process during those early fab-semi collaboration cycles. As foundries were bringing up 28nm processes, KLA-Tencor saw the highest ramp rate in adoption for their latest generation of metrology and inspection systems. Each node is more complex than the previous ones.

The adoption of 20nm will probably not have quite as bad yield ramp as 28nm given that it is a simple process migration without any large changes in the fabrication technology, but we should expect a much slower ramp on 16nm or 14nm, with the introduction of FinFETs, that add a new set of challenges. Brian Trafas, CMO at KLA-Tencor said “you have to be very careful with the control of the side wall of these 3D structures. For example, how do I make sure that I cleaned any residue out of high aspect ratio structure?” We are still finding out the problems that will affect yield at these nodes and it will take a while to discover all of the gotchas and ways to work around them either in the fab technology or in the design rules.

There is another issue facing the fabrication industry. We have become accustomed to Moore’s Law providing a decreasing cost per transistor but that is beginning to break down with the newer geometries. Brian Trafas told me that this is pushing the industry towards adoption of larger wafer sizes, such as 450mm. The cost reduction comes from the fact that many manufacturing steps, such as deposition take the same amount of time independent of the size of the wafer, so while the equipment may cost a little more, the time per step will decrease. This is important because the number of steps is increasing because of the migration to double patterning and this trend is likely to get worse without eUV coming on-line.

I asked him about the possibilities of lower yields on these larger wafers due to variations across the wafer. Brian expects that initially, there will be a tendency to oversample the larger wafers to make certain that the yields are good. If they are not, then we have a problem in that the cost per transistor may not be cheaper. There will be a lot of work to ensure uniformity across the wafer and in fact they are seeing more people wanting to do sampling within a die as well, as well as across a wafer.

Do you have any other visibility into the expected yields ramps for these new nodes?


Brian Bailey – keeping you covered

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