UBM Tech
UBM Tech

Verifying high-speed systems designs

-February 05, 2013

DesignCon is over and if you were lucky enough to be there, you found packed sessions, many standing room only, with engineers looking for ways to deal with the high-frequency designs that aren't just on the horizon but are here now. Back at the exhibits, tools such as Mentor Graphics' latest version of HyperLynx look to provide a faster, more accurate solution. The latest release of HyperLynx offers advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance that's up to 5X faster.

Verifying performance through simulation of a design running at GHz frequencies is truly a challenge both in terms of achieving sufficient fidelity with actual performance and delivering that accuracy quickly in today's short development cycles. With the latest version of HyperLynx, Mentor is tackling that challenge on several fronts. Along with features like DRC using built-in and customer-written rules, HyperLynx users can now use advanced area fill-aware 2.5D planar trace extraction to reduce the amount of channel modeling that requires 3D analysis. Currently, engineers must create their own port assignments to partition a design between planar and 3D analysis, but Mentor has a automatic port assignment tool in the works that should help non-experts take advantage of sophisticated analysis methods. Mentor showed a good result in a correlation study comparing simulated results against measured results for a large layout (see Figure 1).

Figure 1. A correlation study showed comparable eye opening between measured data (left) and results generated with HyperLynx simulation using a 2D/3D channel model extracted from a multi-board system layout using an automated decomposition method.

There's more going on here, particularly in the area of partitioning, analysis, and extraction, but here's a quick look at the features in the new HyperLynx release:
  • Pre-layout DDRx signal integrity and comprehensive cycle-based timing simulation during parametric sweeps. The HyperLynx DDRx wizard supports DDR3L and DDR3U supply levels by incorporating the required derating tables, timing models, and voltage levels, plus test-load compensation of signal launch delays using the DDRx wizard.
  • Batch support of s-parameter models from the post-route environment; interconnect modeling with accurate wideband dielectric models and surface roughness
  • Advanced meshing for DC drop analysis to review accuracy of narrow slivers of metals within complex designs
  • Accelerated simulation flow of IBIS AMI models in statistical mode with LTI equalization algorithms; this feature is based on peak distortion analysis techniques and statistical algorithms that process impulse response of the channel directly for eye diagram generation to quickly produce results for buffers with LTI equalization schemes down to very low BER
  • Improvements to the advanced waveform viewer and processor, a graphical environment for displaying and analyzing large sets of simulation results that has many advanced measurements for complex waveform processing using a rich set of calculator functions. Improvements include an interactive simulation GUI that automatically plots centered eye diagrams.
The new release of HyperLynx ships in March 2013. For more information, visit
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