System update - EDA updates promise stronger, faster design

-May 07, 2013

Cadence Design Systems has announced a new version of its Incisive Enterprise Simulator, offering a 30% improvement in productivity of low-power verification of SoCs, according to the company. The latest release, Version 13.1, includes an updated Incisive SimVision Debugger with new features for visualization and interactive debug of both CPF (Common Power Format) and IEEE 1801 UPF (Unified Power Format) power intent standards. Other upgrades include SystemVerilog support and faster elaboration to turn around simulation jobs much more quickly. For more information, visit Cadence Design Systems.

Synopsys has upgraded its IC Compiler to speed design closure and support the latest process technologies. Synopsys IC Compiler Version 2013.03 now supports final-stage ECOs to close a design in combination with Synopsys PrimeTime. Here, PrimeTime provides signoff-accurate ECO guidance used by IC Compiler with its new minimum physical-impact ECO features to reduce perturbations of the layout in the final stages of development. Along with the compiler's incremental physical verification capability, the minimum physical-impact ECO capability can offer a significant reductino in turnaround time for ECO closure. For more information, visit Synopsys.

Altera addresses the needs of FPGA designers with its latest release of Quartus II software. The new version, Quartus II version 13.0, offers a 25% reduction in compile times for designs targeting its 28mm FPGAs and SoCs and 50% improvement in compile times for designs targeting its 28mm Stratix V FPGAs, according to the company. The new version also offers a number of significant capabilities including:
  • SDK for OpenCL - providing simpler programmable access to FPGA development for software developers (see also: SDK for OpenCL helps software engineers harness FPGA performance)
  • Qsys system integration tool - offering expanded support for ARM-based Cyclone V SoCs
  • DSP Builder design tool - supporting implementation of high-performance fixed- and floating-point algorithms in DSP designs
Both the Subscription Edition and the free Web Edition of Quartus II software v13.0 are now available for download. For more information, visit Altera.
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