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Optimizing autonomous IC test without sacrificing precision

-February 26, 2013

For many years, there was a passionate debate between some DFT practitioners about which is the best test method—logic built-in self test (BIST) or automatic test pattern generation (ATPG).  Recently, the differences between the two have slightly blurred, and now implementations can efficiently share logic between the two approaches.  Thus, for some designs the decision isn’t between using logic BIST or ATPG, but to how to use them together.  I’ll mention the values of each technology and show the advantage of using a hybrid ATPG/BIST method. 

Logic BIST provides a few important advantages compared to other test methods.  One is that the test can be initiated and verified in any test environment, even if an external tester is not available.  This autonomous nature of logic BIST (LBIST) makes it a necessity for field-testing requirements, such as system self-test in a flight control system, satellite, or automobile, as well as some common test environments such as burn-in test.  Another important use of LBIST is for additional detection of “unmodeled” defects for high-quality products. Lastly, LBIST has been very practical for plug-and-play design support. Blocks with LBIST can be reliably reused in any IC without additional run time for pattern generation or risk of unknown coverage. 

ATPG, on the other hand, requires the use of an external tester, but ATPG provides a very high precision of pattern application.  By precision, I mean that ATPG can provide very specific values with each pattern, which lets it apply tests on specific paths or control individual clock gaters throughout the design.  Thus, ATPG can support specialized fault targeting that improves defect detection, including timing-aware, cell-aware, path delay, bridge, and other types of ATPG.  The high number of patterns necessitates the use of embedded compression of the patterns. Today, embedded compression ATPG is the standard approach in most designs, although use of LBIST has been increasing. 

Recently, both compressed ATPG and logic BIST have offered more common features between them. For example, compressed ATPG now supports a type of plug-and-play capability for blocks that is similar to LBIST reuse with pattern retargeting (using block-level patterns at higher levels).  LBIST now supports low-power test similar to what you can do with compressed ATPG.  Also, you can now do multiple input shift register (MISR) diagnosis that has the precision of ATPG but uses the LBIST MISR signatures. 

The demand for LBIST has increased in recent years, and in most of these cases, users also want compressed ATPG for the reasons mentioned above.  As a result, both compressed ATPG and LBIST are increasingly being used together. Using this hybrid ATPG plus LBIST approach has a lot of advantages.  If a user has a requirement for field system test, then this approach will always be taken because you get better test quality of ATPG with autonomous testing of LBIST. One inefficiency of previous applications of both compression ATPG and LBIST is that the LBIST LFSR (linear feedback shift register) and the compression decompressor (as well as MISR and compression compactor) each use different logic, even though their functional purposes are similar. This presented an obvious opportunity to reap big area savings by combining the logic from embedded compression ATPG and LBIST.  This is shown in Figure 1. 


Figure 1.  The logic architecture of a hybrid compression (embedded deterministic test) and logic BIST shares a majority of the decompressor/LFSR and compactor/MSIR logic.  

Another source of area savings with the hybrid approach is that you need to use fewer test points. Sometimes, many test points are added for LBIST to get the required coverage.  However, if ATPG is used with BIST, then you need fewer test points because ATPG can detect the faults that would otherwise require special test points for LBIST to detect.

A second key advantage to the hybrid compression ATPG/LBIST approach is seen in significantly reduced run time. The reduced run time is a consequence of being able to execute LBIST on multiple blocks simultaneously, while ATPG is being applied on one block at a time.  Figure 2 shows the architecture of the hybrid approach, in which compression ATPG and LBIST are shared within each design block, and there is an additional LBIST controller at the top level. 


Figure 2.  The hybrid compressed ATPG/LBIST shares logic within each block and has a top-level LBIST controller to manage clocking and sequences of LBIST tests. 

The LBIST controller is accessed and managed using the IEEE P1687 IJTAG for plug-and-play control.  With the hybrid approach, ATPG only needs to target the faults that are not already detected by LBIST.  As a result, we have seen test time savings in the range of 30%.

About the Author:
Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (design-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching. 

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