Test safety-critical automotive parts
Because semiconductor devices continue to expand in size and complexity, you have to apply more tests in order to ensure detection of all defects. Without the ability to detect all defects, achieving mandated automotive quality levels falls somewhere between difficult and impossible. The increasing number of tests also drives costs higher. To meet quality and control cost, makers of automotive electronics are adopting more efficient test generation solutions. The most popular approach to minimizing logic test costs today is through the use of ATPG compression solutions. The volume of data the testers need to store and apply is greatly reduced with this approach. Compression alone, however, is proving insufficient. You must also generate patterns more intelligently to maximize the defect coverage of each pattern used.
One way to do this is to use the recently developed approach called cell-aware ATPG. Cell-aware test provides significant defect coverage improvements over traditional ATPG with minimal test cost increase. The cell-aware ATPG approach is based on extracting and modeling transistor-level defects from each cell in a technology library. These abstracted defect models are then used during the regular test pattern generation process. Many of these defects, especially those in the more complex library cells, go undetected when using test patterns generated using traditional fault models. Silicon experiments have demonstrated the advantages of using cell-aware ATPG. Results from several real-world designs across multiple technology nodes have shown double and triple digit DPM (defect-per-million) decreases over existing test patterns.
Another way to improve test efficiency and quality is by using a hybrid solution that combines both ATPG compression and logic built-in self test (LBIST) techniques. In this approach, the on-chip logic used for the compression solution and the logic to implement the pseudo-random pattern LBIST are combined and share design-for-test (DFT) resources like scan chains and on-chip clock control. This infrastructure allows any combination of compressed patterns and pseudo-random patterns to be applied.
Using this hybrid approach also gives you several ways to improve test efficiency during manufacturing test. For example, pseudo-random patterns can be used first to cover the faults that are easier to detect. Because stored patterns are no longer needed for these faults, additional tester pattern storage becomes available for targeting faults that are more difficult to detect. The hybrid solution can also reduce the total test time for a complex hierarchical design. Each core is equipped with its own hybrid test infrastructure, which allows it to be tested independently of other cores. When they can be tested independently, they can be tested in parallel, thus reducing overall test time.
Consider, for example, an automotive IC design with four cores. If only ATPG compression were available, then the four cores would have to share the available tester pattern application bandwidth. Each core could either be tested sequentially using all available tester channels or all cores could be tested in parallel with each core using a subset of the channels. However, if each core has both ATPG compression and logic BIST available, then the test for each core can be divided into two phases—ATPG compression used in one phase and LBIST in the other. With this separation, the entire chip can be tested in two phases. In the first phase, two cores use ATPG compression and the other two use LBIST. In the second phase, the situation is reversed. The advantage now is that in each phase, only two cores are sharing all available tester channels, as LBIST does not require patterns from the tester. This means the bandwidth to each core is doubled, so test time is cut in half.
The hybrid compression/LBIST solution plays another critical role related to the ISO 26262 standard. The LBIST capability provides support for in-system test of the device logic. This represents a key capability necessary for addressing the reliability requirements defined by the standard. The LBIST capability can be combined with existing memory BIST capabilities to provide in-system test coverage for most, if not all, of the design. All of the BIST capabilities can generally be accessed through the standard IEEE 1149.1 TAP controller interface. This dedicated interface is sometimes not accessible in-system. To accommodate in-system access, the TAP controller can be enhanced to also support a generic CPU interface that translates between parallel read/write CPU operations and the serial bit sequences required by the TAP protocol (see Figure).
Meeting the quality and reliability requirements of the ISO 26262 and other automotive electronics standards will only become more difficult as device sizes and complexities continue to grow. New advanced test technologies such as cell-aware ATPG and hybrid compression/LBIST provide some key building blocks towards ensuring compliance to the new standards.
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